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Message-ID: <154139982787.88331.4428778114927340653@swboyd.mtv.corp.google.com>
Date: Sun, 04 Nov 2018 22:37:07 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Amit Nischal <anischal@...eaurora.org>,
Michael Turquette <mturquette@...libre.com>
Cc: Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>,
Rajendra Nayak <rnayak@...eaurora.org>,
Odelu Kukatla <okukatla@...eaurora.org>,
Taniya Das <tdas@...eaurora.org>,
linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
Amit Nischal <anischal@...eaurora.org>
Subject: Re: [PATCH v3 4/4] clk: qcom: Add graphics clock controller driver for SDM845
Quoting Amit Nischal (2018-08-12 23:33:07)
> +
> +static int gpu_cc_sdm845_probe(struct platform_device *pdev)
> +{
> + struct regmap *regmap;
> + unsigned int value, mask;
> + int ret;
> +
> + regmap = qcom_cc_map(pdev, &gpu_cc_sdm845_desc);
> + if (IS_ERR(regmap))
> + return PTR_ERR(regmap);
> +
> + clk_fabia_pll_configure(&gpu_cc_pll0, regmap, &gpu_cc_pll0_config);
> + clk_fabia_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config);
> +
> + /*
> + * Configure gpu_cc_cx_gmu_clk with recommended
> + * wakeup/sleep settings
> + */
> + mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
> + mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
> + value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
> + regmap_update_bits(regmap, 0x1098, mask, value);
> +
> + ret = qcom_cc_really_probe(pdev, &gpu_cc_sdm845_desc, regmap);
> + if (ret)
> + return ret;
> +
> + /* Configure clk_dis_wait for gpu_cx_gdsc */
> + regmap_update_bits(regmap, 0x106c, CLK_DIS_WAIT_MASK,
> + 8 << CLK_DIS_WAIT_SHIFT);
Is there a reason this is done after clks are registered? I'd think we
would want to do it before.
> +
> + /* Set supported range of frequencies for gfx3d clock */
> + clk_hw_set_rate_range(&gpu_cc_gx_gfx3d_clk_src.clkr.hw, 180000000,
> + 710000000);
> +
> + return 0;
> +}
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