linux-kernel - Re: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

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Message-ID: <20181105084154.l7g2dp33qlasgnrg@flea>
Date:   Mon, 5 Nov 2018 09:41:54 +0100
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Jagan Teki <jagan@...rulasolutions.com>
Cc:     Chen-Yu Tsai <wens@...e.org>, Icenowy Zheng <icenowy@...c.io>,
        devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com
Subject: Re: [PATCH 1/7] clk: sunxi-ng: sun50i: h6: Fix MMC clock mux width

On Thu, Nov 01, 2018 at 12:06:28AM +0530, Jagan Teki wrote:
> MUX bits for MMC clock register range are 25:24 where 24 is shift
> and 2 is width So fix the width number from 3 to 2.
> 
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>

Applied for 4.21, thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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