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Date: Mon, 5 Nov 2018 16:46:49 +0800
From: Xiaowei Bao <xiaowei.bao@....com>
To: bhelgaas@...gle.com, robh+dt@...nel.org, mark.rutland@....com,
shawnguo@...nel.org, leoyang.li@....com, kishon@...com,
lorenzo.pieralisi@....com, arnd@...db.de,
gregkh@...uxfoundation.org, minghuan.Lian@....com,
mingkai.hu@....com, roy.zang@....com, kstewart@...uxfoundation.org,
cyrille.pitchen@...e-electrons.com, pombredanne@...b.com,
shawn.lin@...k-chips.com, niklas.cassel@...s.com,
linux-pci@...r.kernel.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linuxppc-dev@...ts.ozlabs.org
Cc: Xiaowei Bao <xiaowei.bao@....com>
Subject: [PATCHv2 2/6] ARM: dts: ls1021a: Add the status property disable PCIe
Add the status property disable the PCIe, the property will be enable
by bootloader.
Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
---
v2:
- no change
arch/arm/boot/dts/ls1021a.dtsi | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index bdd6e66..b769e0e 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -736,6 +736,7 @@
<0000 0 0 2 &gic GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
pcie@...0000 {
@@ -759,6 +760,7 @@
<0000 0 0 2 &gic GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 3 &gic GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
<0000 0 0 4 &gic GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>;
+ status = "disabled";
};
can0: can@...0000 {
--
1.7.1
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