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Message-ID: <2da1ff15-1064-3fac-750e-3b0f006ee1af@xilinx.com>
Date: Tue, 6 Nov 2018 12:54:07 +0100
From: Michal Simek <michal.simek@...inx.com>
To: Manish Narani <manish.narani@...inx.com>, <robh+dt@...nel.org>,
<mark.rutland@....com>, <michal.simek@...inx.com>, <bp@...en8.de>,
<mchehab@...nel.org>, <amit.kucheria@...aro.org>,
<sudeep.holla@....com>, <leoyang.li@....com>
CC: <devicetree@...r.kernel.org>, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
<linux-edac@...r.kernel.org>
Subject: Re: [PATCH v10 5/6] arm64: zynqmp: Add DDRC node
On 25. 10. 18 8:07, Manish Narani wrote:
> Add ddrc memory controller node in dts. The size mentioned in dts is
> 0x30000, because we need to access DDR_QOS INTR registers located at
> 0xFD090208 from this driver.
>
> Signed-off-by: Manish Narani <manish.narani@...inx.com>
> ---
> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> index 29ce234..a81d3b16 100644
> --- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> +++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
> @@ -355,6 +355,13 @@
> xlnx,bus-width = <64>;
> };
>
> + mc: memory-controller@...70000 {
> + compatible = "xlnx,zynqmp-ddrc-2.40a";
> + reg = <0x0 0xfd070000 0x0 0x30000>;
> + interrupt-parent = <&gic>;
> + interrupts = <0 112 4>;
> + };
> +
> gem0: ethernet@...b0000 {
> compatible = "cdns,zynqmp-gem", "cdns,gem";
> status = "disabled";
>
Applied with changed subject "arm64: dts: zynqmp: Add DDRC node"
to zynqmp/dt branch.
Thanks,
Michal
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