lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Date:   Tue, 6 Nov 2018 23:07:29 +0530
From:   Vinod Koul <vkoul@...nel.org>
To:     Bjorn Andersson <bjorn.andersson@...aro.org>
Cc:     Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v2 11/17] arm64: dts: qcom: pms405: add gpios

On 05-11-18, 11:08, Bjorn Andersson wrote:
> On Mon 05 Nov 07:45 PST 2018, Vinod Koul wrote:
> 
> > Add the GPIOs present on PMS405 chip.
> > 
> > Signed-off-by: Vinod Koul <vkoul@...nel.org>
> > ---
> >  arch/arm64/boot/dts/qcom/pms405.dtsi | 16 ++++++++++++++++
> >  1 file changed, 16 insertions(+)
> > 
> > diff --git a/arch/arm64/boot/dts/qcom/pms405.dtsi b/arch/arm64/boot/dts/qcom/pms405.dtsi
> > index cdb4547c998b..18410d9f0f8f 100644
> > --- a/arch/arm64/boot/dts/qcom/pms405.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/pms405.dtsi
> > @@ -17,5 +17,21 @@
> >  			reg-names = "rtc", "alarm";
> >  			interrupts = <0x0 0x61 0x1 IRQ_TYPE_NONE>;
> >  		};
> > +
> > +		pms405_gpios: gpios@...0 {
> > +			compatible = "qcom,pms405-gpio";
> > +			reg = <0xc000>;
> > +			gpio-controller;
> > +			#gpio-cells = <2>;
> > +			interrupts = <0 0xc1 0 IRQ_TYPE_NONE>,
> > +				<0 0xc2 0 IRQ_TYPE_NONE>,
> > +				<0 0xc3 0 IRQ_TYPE_NONE>,
> > +				<0 0xc4 0 IRQ_TYPE_NONE>,
> > +				<0 0xc5 0 IRQ_TYPE_NONE>,
> > +				<0 0xc6 0 IRQ_TYPE_NONE>,
> > +				<0 0xc7 0 IRQ_TYPE_NONE>,
> > +				<0 0xca 0 IRQ_TYPE_NONE>,
> > +				<0 0xcb 0 IRQ_TYPE_NONE>;
> 
> Is there a reason why gpio 1, 8 and 9 are omitted from this list?

I think I saw something in downstream code / documentation for this, I
will check again to be sure

-- 
~Vinod

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ