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Message-ID: <20181107100854.28389-1-Zhiqiang.Hou@nxp.com>
Date: Wed, 7 Nov 2018 10:08:59 +0000
From: "Z.q. Hou" <zhiqiang.hou@....com>
To: "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"bhelgaas@...gle.com" <bhelgaas@...gle.com>,
"lorenzo.pieralisi@....com" <lorenzo.pieralisi@....com>,
"jingoohan1@...il.com" <jingoohan1@...il.com>,
"gustavo.pimentel@...opsys.com" <gustavo.pimentel@...opsys.com>
CC: Roy Zang <roy.zang@....com>, Mingkai Hu <mingkai.hu@....com>,
"M.h. Lian" <minghuan.lian@....com>,
"Z.q. Hou" <zhiqiang.hou@....com>
Subject: [PATCHv2 0/4] PCI: dwc: add prefetchable memory range support
From: Hou Zhiqiang <Zhiqiang.Hou@....com>
This patch set is to add prefetchable memory range support, patch 4/4.
Patch 3/4 is to initialize the number of viewport for layerscape PCIe.
BTW, fix 2 bugs, see patch 1/4 and 2/4.
Hou Zhiqiang (4):
PCI: dwc: fix potential memory leak
PCI: dwc: fix 4GiB outbound window size truncated to zero issue
PCI: layerscape: initialize the number of viewport
PCI: dwc: add prefetchable memory range support
drivers/pci/controller/dwc/pci-layerscape.c | 3 +
.../pci/controller/dwc/pcie-designware-host.c | 110 ++++++++++++++----
drivers/pci/controller/dwc/pcie-designware.c | 4 +-
drivers/pci/controller/dwc/pcie-designware.h | 11 +-
4 files changed, 104 insertions(+), 24 deletions(-)
--
2.17.1
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