linux-kernel - [tip:x86/cpu] x86/cpufeatures: Add WBNOINVD feature definition

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Date:   Wed, 7 Nov 2018 13:27:54 -0800
From:   tip-bot for Janakarajan Natarajan <tipbot@...or.com>
To:     linux-tip-commits@...r.kernel.org
Cc:     tglx@...utronix.de, mingo@...nel.org, bp@...e.de, mingo@...hat.com,
        linux-kernel@...r.kernel.org, hpa@...or.com, dwmw@...zon.co.uk,
        r.marek@...embler.cz, Janakarajan.Natarajan@....com,
        fenghua.yu@...el.com, konrad.wilk@...cle.com, x86@...nel.org
Subject: [tip:x86/cpu] x86/cpufeatures: Add WBNOINVD feature definition

Commit-ID:  08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Gitweb:     https://git.kernel.org/tip/08e823c2c5899ef2de3aa1727233f1f19e8c1cc1
Author:     Janakarajan Natarajan <Janakarajan.Natarajan@....com>
AuthorDate: Wed, 7 Nov 2018 20:59:07 +0000
Committer:  Borislav Petkov <bp@...e.de>
CommitDate: Wed, 7 Nov 2018 22:21:03 +0100

x86/cpufeatures: Add WBNOINVD feature definition

Add a new cpufeature definition for the WBNOINVD instruction.

The WBNOINVD instruction writes all modified cache lines in all levels of
the cache associated with a processor to main memory while retaining the
cached values.

Both AMD and Intel support this instruction.

Signed-off-by: Janakarajan Natarajan <Janakarajan.Natarajan@....com>
Signed-off-by: Borislav Petkov <bp@...e.de>
CC: David Woodhouse <dwmw@...zon.co.uk>
CC: Fenghua Yu <fenghua.yu@...el.com>
CC: "H. Peter Anvin" <hpa@...or.com>
CC: Ingo Molnar <mingo@...hat.com>
CC: Konrad Rzeszutek Wilk <konrad.wilk@...cle.com>
CC: Rudolf Marek <r.marek@...embler.cz>
CC: Thomas Gleixner <tglx@...utronix.de>
CC: x86-ml <x86@...nel.org>
Link: http://lkml.kernel.org/r/1541624211-32196-1-git-send-email-Janakarajan.Natarajan@amd.com
---
 arch/x86/include/asm/cpufeatures.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/x86/include/asm/cpufeatures.h b/arch/x86/include/asm/cpufeatures.h
index 28c4a502b419..39a48f06d39d 100644
--- a/arch/x86/include/asm/cpufeatures.h
+++ b/arch/x86/include/asm/cpufeatures.h
@@ -281,6 +281,7 @@
 #define X86_FEATURE_CLZERO		(13*32+ 0) /* CLZERO instruction */
 #define X86_FEATURE_IRPERF		(13*32+ 1) /* Instructions Retired Count */
 #define X86_FEATURE_XSAVEERPTR		(13*32+ 2) /* Always save/restore FP error pointers */
+#define X86_FEATURE_WBNOINVD		(13*32+ 9) /* WBNOINVD instruction */
 #define X86_FEATURE_AMD_IBPB		(13*32+12) /* "" Indirect Branch Prediction Barrier */
 #define X86_FEATURE_AMD_IBRS		(13*32+14) /* "" Indirect Branch Restricted Speculation */
 #define X86_FEATURE_AMD_STIBP		(13*32+15) /* "" Single Thread Indirect Branch Predictors */