linux-kernel - Re: [PATCH 13/36] dt-bindings: arm: Convert PMU binding to json-schema

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Date:   Thu, 8 Nov 2018 16:59:40 +0100
From:   Thomas Petazzoni <thomas.petazzoni@...tlin.com>
To:     Robin Murphy <robin.murphy@....com>
Cc:     Rob Herring <robh@...nel.org>, Will Deacon <will.deacon@....com>,
        Mark Rutland <mark.rutland@....com>,
        devicetree@...r.kernel.org, Kumar Gala <kumar.gala@...aro.org>,
        Grant Likely <glikely@...retlab.ca>,
        Arnd Bergmann <arnd@...db.de>, Tom Rini <trini@...sulko.com>,
        Frank Rowand <frowand.list@...il.com>,
        Linus Walleij <linus.walleij@...aro.org>,
        Pantelis Antoniou <pantelis.antoniou@...sulko.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Bjorn Andersson <bjorn.andersson@...aro.org>,
        Mark Brown <broonie@...nel.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Jonathan Cameron <jic23@...nel.org>,
        Olof Johansson <olof@...om.net>,
        linuxppc-dev <linuxppc-dev@...ts.ozlabs.org>,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>
Subject: Re: [PATCH 13/36] dt-bindings: arm: Convert PMU binding to
 json-schema

Hello,

I'm jumping into the discussion, but I clearly don't have all the
context of the discussion.

On Thu, 8 Nov 2018 15:54:31 +0000, Robin Murphy wrote:

> >> This seems like a semantic different between the two representations, or am
> >> I missing something here? Specifically, both the introduction of
> >> interrupts-extended and also dropping any mention of using a single per-cpu
> >> interrupt (the single combined case is no longer support by Linux; not sure
> >> if you want to keep it in the binding).  
> > 
> > In regards to no support for the single combined interrupt, it looks
> > like Marvell Armada SoCs at least (armada-375 is what I'm looking at)
> > have only a single interrupt. Though the interrupt gets routed to MPIC
> > which then has a GIC PPI. So it isn't supported or happens to work
> > still since it is a PPI?  
> 
> Well, the description of the MPIC in the Armada XP functional spec says:
> 
> "Interrupt sources ID0–ID28 are private events per CPU. Thus, each 
> processor has a different set of events map interrupts ID0–ID28."
> 
> Odd grammar aside, that would seem to imply that <&mpic 3> is a per-cpu 
> interrupt itself, thus AFAICS so long as it's cascaded to a GIC PPI and 
> not an SPI then there's no issue there.

The Armada XP does not have a GIC at all, but only a MPIC as the
primary interrupt controller.

However the Armada 38x has both a GIC and a MPIC, and indeed the parent
interrupts of the MPIC towards the GIC is:

	interrupts = <GIC_PPI 15 IRQ_TYPE_LEVEL_HIGH>;

Best regards,

Thomas
-- 
Thomas Petazzoni, CTO, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com