linux-kernel - Re: [PATCH] RISC-V: recognize S/U mode bits in print

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <mhng-cff31d5f-053e-4e62-997c-232c8bdd5fd3@palmer-si-x1c4>
Date:   Fri, 09 Nov 2018 13:07:03 -0800 (PST)
From:   Palmer Dabbelt <palmer@...ive.com>
To:     me@...ki.ch
CC:     linux-riscv@...ts.infradead.org, me@...ki.ch,
        aou@...s.berkeley.edu, atish.patra@....com, anup@...infault.org,
        linux-kernel@...r.kernel.org
Subject:     Re: [PATCH] RISC-V: recognize S/U mode bits in print_isa

On Fri, 09 Nov 2018 11:33:47 PST (-0800), me@...ki.ch wrote:
> Removes the warning about an unsupported ISA when reading /proc/cpuinfo
> on QEMU.
>
> Signed-off-by: Patrick Stählin <me@...ki.ch>
> ---
>  arch/riscv/kernel/cpu.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 3a5a2ee31547..4029c7e6872b 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -64,7 +64,7 @@ int riscv_of_processor_hartid(struct device_node *node)
>
>  static void print_isa(struct seq_file *f, const char *orig_isa)
>  {
> -	static const char *ext = "mafdc";
> +	static const char *ext = "mafdcsu";
>  	const char *isa = orig_isa;
>  	const char *e;

This is a bit pedantic, but the "S" extension should really be hidden from 
userspace.