linux-kernel - [PATCH 4.19 191/361] cpupower: Fix AMD Family 0x17 msr

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20181111221647.269594606@linuxfoundation.org>
Date:   Sun, 11 Nov 2018 14:18:58 -0800
From:   Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To:     linux-kernel@...r.kernel.org
Cc:     Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable@...r.kernel.org, Prarit Bhargava <prarit@...hat.com>,
        Shuah Khan <shuah@...nel.org>,
        Stafford Horne <shorne@...il.com>,
        Sasha Levin <sashal@...nel.org>
Subject: [PATCH 4.19 191/361] cpupower: Fix AMD Family 0x17 msr_pstate size

4.19-stable review patch.  If anyone has any objections, please let me know.

------------------

From: Prarit Bhargava <prarit@...hat.com>

[ Upstream commit 8c22e2f695920ebd94f9a53bcf2a65eb36d4dba1 ]

The msr_pstate data is only 63 bits long and should be 64 bits.

Add in the missing bit from res1 for AMD Family 0x17.

Reference: https://www.amd.com/system/files/TechDocs/54945_PPR_Family_17h_Models_00h-0Fh.pdf, page 138.

Signed-off-by: Prarit Bhargava <prarit@...hat.com>
Cc: Shuah Khan <shuah@...nel.org>
Cc: Stafford Horne <shorne@...il.com>
Signed-off-by: Shuah Khan (Samsung OSG) <shuah@...nel.org>
Signed-off-by: Sasha Levin <sashal@...nel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
 tools/power/cpupower/utils/helpers/amd.c |    2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

--- a/tools/power/cpupower/utils/helpers/amd.c
+++ b/tools/power/cpupower/utils/helpers/amd.c
@@ -33,7 +33,7 @@ union msr_pstate {
 		unsigned vid:8;
 		unsigned iddval:8;
 		unsigned idddiv:2;
-		unsigned res1:30;
+		unsigned res1:31;
 		unsigned en:1;
 	} fam17h_bits;
 	unsigned long long val;