linux-kernel - Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port clocks

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sun, 11 Nov 2018 19:41:56 -0800
From:   chandanu@...eaurora.org
To:     Stephen Boyd <sboyd@...nel.org>
Cc:     Michael Turquette <mturquette@...libre.com>,
        Taniya Das <tdas@...eaurora.org>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Rajendra Nayak <rnayak@...eaurora.org>,
        linux-arm-msm@...r.kernel.org, linux-soc@...r.kernel.org,
        linux-clk@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-arm-msm-owner@...r.kernel.org
Subject: Re: [PATCH v1 2/2] clk: qcom : dispcc: Add support for display port
 clocks

On 2018-11-06 09:08, Stephen Boyd wrote:
> Quoting Taniya Das (2018-10-31 22:02:22)
>> + Chandan from Display Port team,
>> 
>> On 10/30/2018 10:03 PM, Stephen Boyd wrote:
>> > Also, those
>> > numbers look like gigabits per second (Gbit/s) for the DP spec which
>> > isn't exactly the same as a clk frequency. What frequency does the PLL
>> > run at for these various DP link speeds?
>> >
>> Could you please help with the above query from Stephen?

Hello Stephen,
For DP link speed of 5.4Gbit/s, the PLL will be running at 10.8 Ghz. For 
all
the other DP link speeds, the PLL will be running at 8.1 Ghz.

> 
> Can I safely assume that it matches the link rate shown on Wikipedia 
> for
> display port[1]? I.e.
> 
>  RBR (Reduced Bit Rate): 1.62 Gbit/s bandwidth per lane (162 MHz link
>  symbol rate)
>  HBR (High Bit Rate): 2.70 Gbit/s bandwidth per lane (270 MHz link
>  symbol rate)
>  HBR2 (High Bit Rate 2): 5.40 Gbit/s bandwidth per lane (540 MHz link
>  symbol rate), introduced in DP 1.2
>  HBR3 (High Bit Rate 3): 8.10 Gbit/s bandwidth per lane (810 MHz link
>  symbol rate), introduced in DP 1.3
> 
> So then they're MHz but the table is written in kHz when it should be
> written in Hz. Either way, the table can be removed and then we just
> need to fix the DP PHY PLL code to accept Hz instead of kHz.
> 
> [1] https://en.wikipedia.org/wiki/DisplayPort#Main_link