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Message-ID: <20181113130817.nols3red37yj3yit@flea>
Date:   Tue, 13 Nov 2018 14:08:17 +0100
From:   Maxime Ripard <maxime.ripard@...tlin.com>
To:     Jagan Teki <jagan@...rulasolutions.com>
Cc:     Chen-Yu Tsai <wens@...e.org>, Icenowy Zheng <icenowy@...c.io>,
        Jernej Skrabec <jernej.skrabec@...l.net>,
        Vasily Khoruzhick <anarsoul@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        David Airlie <airlied@...ux.ie>,
        dri-devel@...ts.freedesktop.org,
        Michael Turquette <mturquette@...libre.com>,
        Stephen Boyd <sboyd@...nel.org>, linux-clk@...r.kernel.org,
        Michael Trimarchi <michael@...rulasolutions.com>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, linux-sunxi@...glegroups.com,
        linux-amarula@...rulasolutions.com
Subject: Re: [PATCH v4 01/26] clk: sunxi-ng: a64: Fix gate bit of DSI DPHY

On Tue, Nov 13, 2018 at 04:46:08PM +0530, Jagan Teki wrote:
> DSI DPHY gate bit on MIPI DSI clock register is bit 15
> not bit 30.
> 
> Signed-off-by: Jagan Teki <jagan@...rulasolutions.com>
> Acked-by: Stephen Boyd <sboyd@...nel.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

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