| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-Id: <20181114090027.7580-4-benjamin.gaignard@linaro.org>
Date: Wed, 14 Nov 2018 10:00:26 +0100
From: Benjamin Gaignard <benjamin.gaignard@...aro.org>
To: ohad@...ery.com, bjorn.andersson@...aro.org, robh+dt@...nel.org,
mark.rutland@....com, alexandre.torgue@...com
Cc: linux-remoteproc@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
Benjamin Gaignard <benjamin.gaignard@...com>,
Benjamin Gaignard <benjamin.gaignard@...aro.org>
Subject: [PATCH v4 3/4] ARM: dts: stm32: Add hwspinlock node for stm32mp157 SoC
From: Benjamin Gaignard <benjamin.gaignard@...com>
Declare hwspinlock device for stm32mp157 SoC
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...com>
Signed-off-by: Benjamin Gaignard <benjamin.gaignard@...aro.org>
---
arch/arm/boot/dts/stm32mp157c.dtsi | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/arch/arm/boot/dts/stm32mp157c.dtsi b/arch/arm/boot/dts/stm32mp157c.dtsi
index 185541a5b69f..98f824d8b0f0 100644
--- a/arch/arm/boot/dts/stm32mp157c.dtsi
+++ b/arch/arm/boot/dts/stm32mp157c.dtsi
@@ -803,6 +803,15 @@
status = "disabled";
};
+ hsem: hwspinlock@...00000 {
+ compatible = "st,stm32-hwspinlock";
+ #hwlock-cells = <1>;
+ reg = <0x4c000000 0x400>;
+ clocks = <&rcc HSEM>;
+ clock-names = "hwsem";
+ status = "disabled";
+ };
+
rcc: rcc@...00000 {
compatible = "st,stm32mp1-rcc", "syscon";
reg = <0x50000000 0x1000>;
--
2.15.0
Powered by blists - more mailing lists