linux-kernel - Re: [PATCH] rtc: m41t80: Complete error propagation from SMBus calls

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Date:   Wed, 14 Nov 2018 12:50:06 +0000 (GMT)
From:   "Maciej W. Rozycki" <macro@...ux-mips.org>
To:     Alexandre Belloni <alexandre.belloni@...tlin.com>
cc:     Alessandro Zummo <a.zummo@...ertech.it>,
        Matt Turner <mattst88@...il.com>, linux-rtc@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH] rtc: m41t80: Complete error propagation from SMBus
 calls

On Wed, 14 Nov 2018, Alexandre Belloni wrote:

> >  I think we can discuss that when I post the patches.  The m41t80 driver 
> > currently does not work for me anyway and has to be fixed because of:
> > 
> > i2c /dev entries driver
> > i2c-sibyte: i2c SMBus adapter module for SiByte board
> > i2c i2c-1: doesn't support I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_I2C_BLOCK
> > 
> > and the persistent part is only one patch in the upcoming number of 
> > changes.
> 
> Well, one of the solution for that (and tis is on my todo list) is to
> convert the driver to use regmap which would take care of using the
> proper i2c transfers. However, one of the concern when not having bock
> accesses is that the registers are not latched (as you seem to know).
> One thing I would like is then to avoid the multiple SEC register read
> when not necessary.

 Unfortunately the SMBus host does not give much choice here.  It does 
have some extensions for block transfers, but writes are limited to 5 
bytes and reads to 7 bytes.  The usual solution is to read repeatedly 
until the seconds match.  For writes it is not a problem, because it 
takes less than 1 second to write all the clock registers, so if you 
start with seconds, then the data written will be consistent.

 The Xicor chip is worse as it uses 16-bit addresses and that is not 
handled by SMBus support in our I2C core, however apparently that can be 
simulated by byte writes with that particular chip.  The SMBus host 
implements a protocol extension for 16-bit addressing, but I think it's 
not worth the hassle adding to SMBus support in our I2C core given how 
rare the Xicor setup are.

 Finally the SMBus host does support raw I2C transfers, but only with a 
polled bit-banged interface, where you need to time the loop correctly 
to get clocking of the individual bits right.  I don't think we want to 
go down that path.

  Maciej