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Message-ID: <a000e296-7d7f-6a98-3869-3b476101749e@intel.com>
Date: Wed, 14 Nov 2018 16:40:51 -0800
From: Dave Hansen <dave.hansen@...el.com>
To: Keith Busch <keith.busch@...el.com>, linux-kernel@...r.kernel.org,
linux-acpi@...r.kernel.org, linux-mm@...ck.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
Rafael Wysocki <rafael@...nel.org>,
Dan Williams <dan.j.williams@...el.com>
Subject: Re: [PATCH 4/7] node: Add memory caching attributes
On 11/14/18 2:49 PM, Keith Busch wrote:
> System memory may have side caches to help improve access speed. While
> the system provided cache is transparent to the software accessing
> these memory ranges, applications can optimize their own access based
> on cache attributes.
>
> In preparation for such systems, provide a new API for the kernel to
> register these memory side caches under the memory node that provides it.
>
> The kernel's sysfs representation is modeled from the cpu cacheinfo
> attributes, as seen from /sys/devices/system/cpu/cpuX/cache/. Unlike CPU
> cacheinfo, though, a higher node's memory cache level is nearer to the
> CPU, while lower levels are closer to the backing memory. Also unlike
> CPU cache, the system handles flushing any dirty cached memory to the
> last level the memory on a power failure if the range is persistent.
>
> The exported attributes are the cache size, the line size, associativity,
> and write back policy.
Could you also include an example of the layout?
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