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Date: Mon, 19 Nov 2018 17:28:18 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org,
Chris Packham <chris.packham@...iedtelesis.co.nz>,
Stephen Boyd <sboyd@...nel.org>,
Sudip Mukherjee <sudipm.mukherjee@...il.com>
Subject: [PATCH 4.14 044/124] clk: mvebu: use correct bit for 98DX3236 NAND
4.14-stable review patch. If anyone has any objections, please let me know.
------------------
From: Chris Packham <chris.packham@...iedtelesis.co.nz>
commit 00c5a926af12a9f0236928dab3dc9faf621406a1 upstream.
The correct fieldbit value for the NAND PLL reload trigger is 27.
Fixes: commit e120c17a70e5 ("clk: mvebu: support for 98DX3236 SoC")
Signed-off-by: Chris Packham <chris.packham@...iedtelesis.co.nz>
Signed-off-by: Stephen Boyd <sboyd@...nel.org>
Signed-off-by: Sudip Mukherjee <sudipm.mukherjee@...il.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
---
drivers/clk/mvebu/clk-corediv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
--- a/drivers/clk/mvebu/clk-corediv.c
+++ b/drivers/clk/mvebu/clk-corediv.c
@@ -72,7 +72,7 @@ static const struct clk_corediv_desc mve
};
static const struct clk_corediv_desc mv98dx3236_corediv_desc[] = {
- { .mask = 0x0f, .offset = 6, .fieldbit = 26 }, /* NAND clock */
+ { .mask = 0x0f, .offset = 6, .fieldbit = 27 }, /* NAND clock */
};
#define to_corediv_clk(p) container_of(p, struct clk_corediv, hw)
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