linux-kernel - Re: [REGRESSION] x86, perf: counter freezing breaks rr

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 20 Nov 2018 14:19:01 -0800
From:   Andi Kleen <ak@...ux.intel.com>
To:     Kyle Huey <me@...ehuey.com>
Cc:     Kan Liang <kan.liang@...ux.intel.com>,
        "Peter Zijlstra (Intel)" <peterz@...radead.org>,
        Ingo Molnar <mingo@...nel.org>,
        Robert O'Callahan <robert@...llahan.org>,
        Alexander Shishkin <alexander.shishkin@...ux.intel.com>,
        Arnaldo Carvalho de Melo <acme@...hat.com>,
        Jiri Olsa <jolsa@...hat.com>,
        Linus Torvalds <torvalds@...ux-foundation.org>,
        Stephane Eranian <eranian@...gle.com>,
        Thomas Gleixner <tglx@...utronix.de>,
        Vince Weaver <vincent.weaver@...ne.edu>, acme@...nel.org,
        open list <linux-kernel@...r.kernel.org>
Subject: Re: [REGRESSION] x86, perf: counter freezing breaks rr

On Tue, Nov 20, 2018 at 01:46:05PM -0800, Kyle Huey wrote:
> On Tue, Nov 20, 2018 at 1:18 PM Andi Kleen <ak@...ux.intel.com> wrote:
> >
> > > I suppose that's fair that it's better for some use cases. The flip
> > > side is that it's no longer possible to get exactly accurate counts
> > > from user space if you're using the PMI (because any events between
> > > the overflow itself and the transition to the PMI handler are
> > > permanently lost) which is catastrophically bad for us :)
> >
> > Yes that's a fair point. For most usages it doesn't matter.
> >
> > I suspect that's a case for supporting opt-out for freezing
> > per perf event, and rr using that.
> 
> I don't see how you could easily opt-out on a per perf event basis. If
> I'm reading the SDM correctly the Freeze_PerfMon_On_PMI setting is
> global and affects all counters on that CPU. Even counters that don't
> use the PMI at all will still be frozen if another counter overflows
> and counter freezing is enabled. It would seem that a counter that
> wants to use counter freezing and a counter that wants the behavior we
> want would be mutually exclusive. I suppose the kernel could handle
> all of that but it's a bit involved.

Yes it's a per CPU setting.  You wouldn't be able to opt-in. If anyone opts
out on a CPU it would be disabled on that CPU while that event
is active.

-Andi