linux-kernel - Re: [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT

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Message-ID: <CAD=FV=XD7g8gZsTNTLGCN3ZC7zOuFX1LxMWVnE+=1k68tuQVpg@mail.gmail.com>
Date:   Tue, 20 Nov 2018 14:41:03 -0800
From:   Doug Anderson <dianders@...omium.org>
To:     Matthias Kaehlcke <mka@...omium.org>
Cc:     Rob Clark <robdclark@...il.com>, David Airlie <airlied@...ux.ie>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Archit Taneja <architt@...eaurora.org>,
        Sean Paul <seanpaul@...omium.org>,
        Rajesh Yadav <ryadav@...eaurora.org>,
        Stephen Boyd <swboyd@...omium.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        freedreno <freedreno@...ts.freedesktop.org>,
        devicetree@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 2/2] drm/msm/dsi: Get PHY ref clock from the DT

Hi,

On Wed, Nov 14, 2018 at 3:56 PM Matthias Kaehlcke <mka@...omium.org> wrote:
>
> On Thu, Nov 08, 2018 at 02:04:31PM -0800, Doug Anderson wrote:
> > Hi,
> >
> > On Fri, Nov 2, 2018 at 2:45 PM Matthias Kaehlcke <mka@...omium.org> wrote:
> > >
> > > Get the PHY ref clock from the device tree instead of hardcoding
> > > its name and rate.
> > >
> > > Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> > > ---
> > >  drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 11 ++++++++++-
> > >  1 file changed, 10 insertions(+), 1 deletion(-)
> > >
> > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > > index 4c03f0b7343ed..1016eb50df8f5 100644
> > > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
> > > @@ -91,6 +91,8 @@ struct dsi_pll_10nm {
> > >         void __iomem *phy_cmn_mmio;
> > >         void __iomem *mmio;
> > >
> > > +       struct clk *vco_ref_clk;
> > > +
> > >         u64 vco_ref_clk_rate;
> > >         u64 vco_current_rate;
> > >
> > > @@ -630,7 +632,8 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
> > >         char clk_name[32], parent[32], vco_name[32];
> > >         char parent2[32], parent3[32], parent4[32];
> > >         struct clk_init_data vco_init = {
> > > -               .parent_names = (const char *[]){ "xo" },
> > > +               .parent_names = (const char *[]){
> > > +                       __clk_get_name(pll_10nm->vco_ref_clk) },
> > >                 .num_parents = 1,
> > >                 .name = vco_name,
> > >                 .flags = CLK_IGNORE_UNUSED,
> > > @@ -786,6 +789,12 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
> > >         pll_10nm->id = id;
> > >         pll_10nm_list[id] = pll_10nm;
> > >
> > > +       pll_10nm->vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
> > > +       if (IS_ERR(pll_10nm->vco_ref_clk)) {
> > > +               dev_err(&pdev->dev, "couldn't get 'ref' clock\n");
> > > +               return (void *)pll_10nm->vco_ref_clk;
> > > +       }
> >
> > So, ummmm.  Can you follow the same pattern for all the other clocks
> > in this file too?  All parents should get their name based on
> > references in the device tree.
> >
> > It turns out that right now we have a mismatch because
> > "drivers/clk/qcom/dispcc-sdm845.c" calls "dsi0pllbyte"
> > "dsi0_phy_pll_out_byteclk" and calls "dsi0pll"
> > "dsi0_phy_pll_out_dsiclk".  We might want to change the names in
> > dispcc-sdm845.c, but it wouldn't matter if we simply didn't hardcode
> > them here.
>
> Hm, I understand the problem, but not quite what you mean with 'follow
> the same pattern'. The VCO ref clock is an 'external'/existing clock,
> hence it can be specificed in the DT and obtained with
> _clk_get(). However the clocks you mention above are 'created' by the
> PHY driver, so we could only specify their names in the DT, not sure
> if that's what you are suggesting. I guess 'clock-output-names' could
> be used, though it isn't really useful to describe the names in a
> clock tree. If you still think this should be done please share how
> you envision the DT entries to look.

Ah.  Right.  This is me being dumb.  As you said the
"dsi0_phy_pll_out_byteclk" and "dsi0_phy_pll_out_dsiclk" clocks are
backwards of the one you're dealing with here.  No no change needed in
your patch for this.

In theory we could do a follow-up patch where the dispcc-sdm845
bindings take phandle references to the PHY clock for the clocks it
consumes.  That would future proof the bindings but I believe it
wouldn't really be possible to use them right now in code since the
clock framework doesn't really handle cases where two drivers mutually
produce / consume clocks from each other.


-Doug