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Message-ID: <CAK8P3a1Gszsg7Wky+7Z8TuOtAtZR2ia-QjYm01-wWKRmYfdm7Q@mail.gmail.com>
Date: Wed, 21 Nov 2018 21:11:52 +0100
From: Arnd Bergmann <arnd@...db.de>
To: Vineet Gupta <vineet.gupta1@...opsys.com>
Cc: Vitor Soares <vitor.soares@...opsys.com>,
alexey.brodkin@...opsys.com, Joao Pinto <joao.pinto@...opsys.com>,
jose.abreu@...opsys.com,
"open list:SYNOPSYS ARC ARCHITECTURE"
<linux-snps-arc@...ts.infradead.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>
Subject: Re: Misaligned Access
On Wed, Nov 21, 2018 at 8:42 PM Vineet Gupta <vineet.gupta1@...opsys.com> wrote:
>
> +CC lkml, Arnd : subject matter expert
>
> On 11/21/18 10:06 AM, Vitor Soares wrote:
> > I use the follow function to get data from a RX Fifo.
> >
> >
> > static void dw_i3c_master_read_rx_fifo(struct dw_i3c_master *master,
> > u8 *bytes, int nbytes)
> > {
> > readsl(master->regs + RX_TX_DATA_PORT, bytes, nbytes / 4);
>
> So the semantics are reading the same fifo register N times, to get the N words,
> hence read*s*l is appropriate. That however expects the buffer to be 4 bytes
> aligned, hence your issue. You can't possibly use the reads*b* as we want the
>
> The obvious but crude hack is to use a temp array for readsl and then copy over
> using memcpy, but I'm sure there are better ways, @Arnd ? To summarize is issue is
> a driver triggering unaligned access due to the misinteraction of API (driver get
> an unaligned u8 *) which goes against expectations of io accessor readl (needed
> since the register contents are 4 bytes)
Is this again on ARC or some other architecture that cannot do unaligned
access to normal RAM? On ARMv7 or x86, you should never see a problem
because the CPU handles misaligned writes. On ARMv4/v5, the readsl()
implementation internally aligns the access to the output buffer so it
will work correctly.
Arnd
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