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Message-Id: <20181126105100.912940259@linuxfoundation.org>
Date: Mon, 26 Nov 2018 11:50:21 +0100
From: Greg Kroah-Hartman <gregkh@...uxfoundation.org>
To: linux-kernel@...r.kernel.org
Cc: Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
stable@...r.kernel.org, Jianxin Qin <jianxin.qin@...ogic.com>,
Yixun Lan <yixun.lan@...ogic.com>,
Jerome Brunet <jbrunet@...libre.com>,
Sasha Levin <sashal@...nel.org>
Subject: [PATCH 4.19 027/118] clk: meson-axg: pcie: drop the mpll3 clock parent
4.19-stable review patch. If anyone has any objections, please let me know.
------------------
[ Upstream commit 69b93104c7ec5668019caf5d2dbfd0e182df06db ]
We found the PCIe driver doesn't really work with
the mpll3 clock which is actually reserved for debug,
So drop it from the mux list.
Fixes: 33b89db68236 ("clk: meson-axg: add clocks required by pcie driver")
Tested-by: Jianxin Qin <jianxin.qin@...ogic.com>
Signed-off-by: Yixun Lan <yixun.lan@...ogic.com>
Signed-off-by: Jerome Brunet <jbrunet@...libre.com>
Signed-off-by: Sasha Levin <sashal@...nel.org>
---
drivers/clk/meson/axg.c | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/meson/axg.c b/drivers/clk/meson/axg.c
index 8cf74fc423e6..baabcf7c0a24 100644
--- a/drivers/clk/meson/axg.c
+++ b/drivers/clk/meson/axg.c
@@ -713,12 +713,14 @@ static struct clk_regmap axg_pcie_mux = {
.offset = HHI_PCIE_PLL_CNTL6,
.mask = 0x1,
.shift = 2,
+ /* skip the parent mpll3, reserved for debug */
+ .table = (u32[]){ 1 },
},
.hw.init = &(struct clk_init_data){
.name = "pcie_mux",
.ops = &clk_regmap_mux_ops,
- .parent_names = (const char *[]){ "mpll3", "pcie_pll" },
- .num_parents = 2,
+ .parent_names = (const char *[]){ "pcie_pll" },
+ .num_parents = 1,
.flags = CLK_SET_RATE_PARENT,
},
};
--
2.17.1
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