lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <CAD=FV=VXo+cifBpdFm4WoOd6pgtdREvhWCR6QPWR3219kcU8fg@mail.gmail.com>
Date:   Tue, 27 Nov 2018 22:18:27 -0800
From:   Doug Anderson <dianders@...omium.org>
To:     Matthias Kaehlcke <mka@...omium.org>
Cc:     Rob Clark <robdclark@...il.com>, David Airlie <airlied@...ux.ie>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Andy Gross <andy.gross@...aro.org>,
        David Brown <david.brown@...aro.org>,
        Archit Taneja <architt@...eaurora.org>,
        Sean Paul <seanpaul@...omium.org>,
        Rajesh Yadav <ryadav@...eaurora.org>,
        Stephen Boyd <swboyd@...omium.org>,
        Jeykumar Sankaran <jsanka@...eaurora.org>,
        linux-arm-msm <linux-arm-msm@...r.kernel.org>,
        dri-devel <dri-devel@...ts.freedesktop.org>,
        freedreno <freedreno@...ts.freedesktop.org>,
        devicetree@...r.kernel.org, LKML <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v2 5/7] drm/msm/dsi: 28nm PHY: Get ref clock from the DT

Hi,

On Mon, Nov 26, 2018 at 3:12 PM Matthias Kaehlcke <mka@...omium.org> wrote:
>
> Get the ref clock of the PHY from the device tree instead of
> hardcoding its name and rate.
>
> Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
> ---
> Changes in v2:
> - patch added to the series
> ---
>  drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 29 +++++++++++++++-------
>  1 file changed, 20 insertions(+), 9 deletions(-)

Generally same feedback as with "28nm 8960 PHY" patch, plus...


> @@ -81,6 +80,7 @@ struct dsi_pll_28nm {
>         struct platform_device *pdev;
>         void __iomem *mmio;
>
> +       struct clk *vco_ref_clk;
>         int vco_delay;
>
>         /* private clocks: */
> @@ -139,6 +139,7 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
>         struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
>         struct device *dev = &pll_28nm->pdev->dev;
>         void __iomem *base = pll_28nm->mmio;
> +       u64 ref_clk_rate = parent_rate;

Are you sure it's good to stash this in a u64 instead of just using
the parent_rate directly?

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ