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Message-ID: <20181128091642.GC17419@ulmo>
Date: Wed, 28 Nov 2018 10:16:42 +0100
From: Thierry Reding <thierry.reding@...il.com>
To: Robert Yang <decatf@...il.com>
Cc: Peter De Schrijver <pdeschrijver@...dia.com>,
Prashant Gaikwad <pgaikwad@...dia.com>,
Michael Turquette <mturquette@...libre.com>,
Stephen Boyd <sboyd@...nel.org>,
Jonathan Hunter <jonathanh@...dia.com>,
linux-clk@...r.kernel.org, linux-tegra@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH V2] clk: tegra: Return the exact clock rate from
clk_round_rate
On Tue, Sep 25, 2018 at 05:49:40PM -0400, Robert Yang wrote:
> The current behavior is that clk_round_rate would return the same clock
> rate passed to it for valid PLL configurations. This change will return
> the exact rate the PLL will provide in accordance with clk API.
>
> Signed-off-by: Robert Yang <decatf@...il.com>
> ---
> Changes in V2:
> - Move input divider (m == 0) check into the cfg constraints check
> condition. Forgo adding WARN_ON and avoid using 0 input divider
> all together.
>
> drivers/clk/tegra/clk-pll.c | 7 ++++---
> 1 file changed, 4 insertions(+), 3 deletions(-)
Acked-by: Thierry Reding <treding@...dia.com>
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