linux-kernel - Re: 答复: [RFC] locking/rwsem: Avoid issuing wakeup before setting the reader waiter to nil

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-ID: <20181130141544.GK11632@hirez.programming.kicks-ass.net>
Date:   Fri, 30 Nov 2018 15:15:44 +0100
From:   Peter Zijlstra <peterz@...radead.org>
To:     "Liu,Qi(ACU-T1)" <liuqi16@...du.com>
Cc:     Waiman Long <longman@...hat.com>,
        Will Deacon <will.deacon@....com>,
        Yongji Xie <elohimes@...il.com>,
        "mingo@...hat.com" <mingo@...hat.com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Xie,Yongji" <xieyongji@...du.com>,
        "Zhang,Yu(ACU-T1)" <zhangyu31@...du.com>,
        "Yuan,Linsi" <yuanlinsi01@...du.com>, "Ni,Xun" <nixun@...du.com>,
        "Li,Lin(ACU-T1)" <lilin24@...du.com>,
        Davidlohr Bueso <dave@...olabs.net>
Subject: Re: 答复: [RFC] locking/rwsem: Avoid issuing wakeup before setting the
 reader waiter to nil

On Fri, Nov 30, 2018 at 09:34:19AM +0000, Liu,Qi(ACU-T1) wrote:
> Is there a semantic divergence between x86 instruction "LOCK cmpxchg"
> and the macro cmpxchg defined in linux kernel? The former guarantee
> full barrier in any case, and the latter only imply barrier in case of
> success?

> So, we use 	
>     smp_mb__before_atomic()
> 	cmpxchg_relaxed()  // no barrier
> to get rid of the redundant barrier
>    smp_mb__before_atomic()
>    cmpxchg()          // imply a redundant barrier when successing  

No, it is all horribly more complicated :-)

On x86: cmpxchg_relaxed() == cmpxchg() == LOCK CMPXCHG, however
smp_mb__{before,after}_atomic() is a no-op.

On say arm OTOH: cmpxchg_relaxed() == LL/SC, but then
smp_mb__{before,after}_atomic() is smp_mb(), such that: cmpxchg() := {
smp_mb__before_atomic(); cmpxchg_relaxed(); smp_mb__after_atomic(); }

The difference is that on x86 atomic instructions unconditionally imply
memory ordering; whereas on ARM they do not.