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Message-ID: <d1e4cb48-1952-fb61-bd2b-db9efe3b5f1a@amd.com>
Date:   Fri, 30 Nov 2018 14:52:26 +0000
From:   "StDenis, Tom" <Tom.StDenis@....com>
To:     Peter Zijlstra <peterz@...radead.org>,
        "dave.hansen@...el.com" <dave.hansen@...el.com>,
        "luto@...nel.org" <luto@...nel.org>
CC:     "x86@...nel.org" <x86@...nel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "Deucher, Alexander" <Alexander.Deucher@....com>
Subject: Re: [PATCH 0/4] x86/mm/cpa: Fix cpa-array TLB invalidation

Hi Peter,

Unfortunately I can't apply this on top of our drm-next the first patch 
fails.

Alex: could we rebase again at some point?

Tom

On 2018-11-30 8:44 a.m., Peter Zijlstra wrote:
> Hi,
> 
> Yesterday Tom reported a CPA bug triggered by the AMDGPU team.
> 
> It turns out that with commit:
> 
>    a7295fd53c39 ("x86/mm/cpa: Use flush_tlb_kernel_range()")
> 
> I misread the cpa array code and messed up the TLB invalidations for it. These
> patches (hopefully) fix the issue while also shrinking the CPA code again.
> 
> Tom, would you be so kind as to test again? These patches are significantly
> different from what I send you yesterday.
> 
> ---
> arch/x86/mm/mm_internal.h |   2 +
> arch/x86/mm/pageattr.c    | 167 ++++++++++++++++++++--------------------------
> arch/x86/mm/tlb.c         |   4 +-
> 3 files changed, 79 insertions(+), 94 deletions(-)
> 

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