linux-kernel - Re: [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC

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Message-ID: <20181130180702.GL43329@arrakis.emea.arm.com>
Date:   Fri, 30 Nov 2018 18:07:04 +0000
From:   Catalin Marinas <Catalin.Marinas@....com>
To:     Julien Thierry <Julien.Thierry@....com>
CC:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "daniel.thompson@...aro.org" <daniel.thompson@...aro.org>,
        Marc Zyngier <Marc.Zyngier@....com>,
        Suzuki Poulose <Suzuki.Poulose@....com>,
        Will Deacon <Will.Deacon@....com>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Christoffer Dall <Christoffer.Dall@....com>,
        James Morse <James.Morse@....com>,
        "joel@...lfernandes.org" <joel@...lfernandes.org>
Subject: Re: [PATCH v6 02/24] arm64: cpufeature: Set SYSREG_GIC_CPUIF as a
 boot system feature

On Mon, Nov 12, 2018 at 11:56:53AM +0000, Julien Thierry wrote:
> It is not supported to have some CPUs using GICv3 sysreg CPU interface
> while some others do not.
>
> Once ICC_SRE_EL1.SRE is set on a CPU, the bit cannot be cleared. Since
> matching this feature require setting ICC_SRE_EL1.SRE, it cannot be
> turned off if found on a CPU.
>
> Set the feature as STRICT_BOOT, if boot CPU has it, all other CPUs are
> required to have it.
>
> Signed-off-by: Julien Thierry <julien.thierry@....com>
> Suggested-by: Daniel Thompson <daniel.thompson@...aro.org>
> Cc: Catalin Marinas <catalin.marinas@....com>
> Cc: Will Deacon <will.deacon@....com>
> Cc: Suzuki K Poulose <suzuki.poulose@....com>
> Cc: Marc Zyngier <marc.zyngier@....com>

Acked-by: Catalin Marinas <catalin.marinas@....com>
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