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Message-Id: <20181201005254.139908-4-mka@chromium.org>
Date: Fri, 30 Nov 2018 16:52:49 -0800
From: Matthias Kaehlcke <mka@...omium.org>
To: Rob Clark <robdclark@...il.com>, David Airlie <airlied@...ux.ie>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>
Cc: Archit Taneja <architt@...eaurora.org>,
Sean Paul <seanpaul@...omium.org>,
Rajesh Yadav <ryadav@...eaurora.org>,
Douglas Anderson <dianders@...omium.org>,
Stephen Boyd <swboyd@...omium.org>,
Jeykumar Sankaran <jsanka@...eaurora.org>,
linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org, Matthias Kaehlcke <mka@...omium.org>
Subject: [PATCH v3 3/8] drm/msm/dsi: 28nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate. Use default values if the ref
clock is not specified.
Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
---
Changes in v3:
- use default name and rate if the ref clock is not specified
in the DT
- store vco_ref_clk_name instead of vco_ref_clk
- dsi_pll_28nm_clk_set_rate: changed data type of ref_clk_rate to
unsigned long
- fixed check for EPROBE_DEFER
- renamed VCO_REF_CLK_RATE to VCO_REF_CLK_DEFAULT_RATE
Changes in v2:
- patch added to the series
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 35 ++++++++++++++++------
1 file changed, 26 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
index 26e3a01a99c2b..4a84c69ca0b2b 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c
@@ -40,7 +40,7 @@
#define NUM_PROVIDED_CLKS 2
-#define VCO_REF_CLK_RATE 19200000
+#define VCO_REF_CLK_DEFAULT_RATE 19200000
#define VCO_MIN_RATE 350000000
#define VCO_MAX_RATE 750000000
@@ -81,6 +81,7 @@ struct dsi_pll_28nm {
struct platform_device *pdev;
void __iomem *mmio;
+ const char *vco_ref_clk_name;
int vco_delay;
/* private clocks: */
@@ -139,6 +140,8 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll);
struct device *dev = &pll_28nm->pdev->dev;
void __iomem *base = pll_28nm->mmio;
+ unsigned long ref_clk_rate = parent_rate ?
+ parent_rate : VCO_REF_CLK_DEFAULT_RATE;
unsigned long div_fbx1000, gen_vco_clk;
u32 refclk_cfg, frac_n_mode, frac_n_value;
u32 sdm_cfg0, sdm_cfg1, sdm_cfg2, sdm_cfg3;
@@ -166,17 +169,17 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate,
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC1_CFG, 0x70);
pll_write(base + REG_DSI_28nm_PHY_PLL_LPFC2_CFG, 0x15);
- rem = rate % VCO_REF_CLK_RATE;
+ rem = rate % ref_clk_rate;
if (rem) {
refclk_cfg = DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
frac_n_mode = 1;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 500);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 500);
+ div_fbx1000 = rate / (ref_clk_rate / 500);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 500);
} else {
refclk_cfg = 0x0;
frac_n_mode = 0;
- div_fbx1000 = rate / (VCO_REF_CLK_RATE / 1000);
- gen_vco_clk = div_fbx1000 * (VCO_REF_CLK_RATE / 1000);
+ div_fbx1000 = rate / (ref_clk_rate / 1000);
+ gen_vco_clk = div_fbx1000 * (ref_clk_rate / 1000);
}
DBG("refclk_cfg = %d", refclk_cfg);
@@ -265,7 +268,8 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
void __iomem *base = pll_28nm->mmio;
u32 sdm0, doubler, sdm_byp_div;
u32 sdm_dc_off, sdm_freq_seed, sdm2, sdm3;
- u32 ref_clk = VCO_REF_CLK_RATE;
+ u32 ref_clk = parent_rate ?
+ parent_rate : VCO_REF_CLK_DEFAULT_RATE;
unsigned long vco_rate;
VERB("parent_rate=%lu", parent_rate);
@@ -273,7 +277,7 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw,
/* Check to see if the ref clk doubler is enabled */
doubler = pll_read(base + REG_DSI_28nm_PHY_PLL_REFCLK_CFG) &
DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR;
- ref_clk += (doubler * VCO_REF_CLK_RATE);
+ ref_clk += (doubler * ref_clk);
/* see if it is integer mode or sdm mode */
sdm0 = pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG0);
@@ -518,7 +522,7 @@ static int pll_28nm_register(struct dsi_pll_28nm *pll_28nm)
{
char clk_name[32], parent1[32], parent2[32], vco_name[32];
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = &pll_28nm->vco_ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -593,6 +597,7 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
{
struct dsi_pll_28nm *pll_28nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
int ret;
if (!pdev)
@@ -605,6 +610,18 @@ struct msm_dsi_pll *msm_dsi_pll_28nm_init(struct platform_device *pdev,
pll_28nm->pdev = pdev;
pll_28nm->id = id;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (!IS_ERR(vco_ref_clk)) {
+ pll_28nm->vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+ } else {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret == -EPROBE_DEFER)
+ ERR_PTR(ret);
+
+ dev_warn(&pdev->dev, "'ref' clock is not specified, using default name\n");
+ pll_28nm->vco_ref_clk_name = "xo";
+ }
+
pll_28nm->mmio = msm_ioremap(pdev, "dsi_pll", "DSI_PLL");
if (IS_ERR_OR_NULL(pll_28nm->mmio)) {
dev_err(&pdev->dev, "%s: failed to map pll base\n", __func__);
--
2.20.0.rc1.387.gf8505762e3-goog
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