linux-kernel - Re: [PATCH v1 05/12] usb: dwc3: Add two quirks for Hisilicon Kirin Soc Platform

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Message-ID: <CAHp75VcbNumAGa8NsYp9tL-ZRP4stApuTFtY1LARHMnJjxA4dw@mail.gmail.com>
Date:   Mon, 3 Dec 2018 10:02:49 +0200
From:   Andy Shevchenko <andy.shevchenko@...il.com>
To:     chenyu56@...wei.com
Cc:     USB <linux-usb@...r.kernel.org>,
        devicetree <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Suzhuangluan <suzhuangluan@...ilicon.com>,
        Kongfei <kongfei@...ilicon.com>, Felipe Balbi <balbi@...nel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        John Stultz <john.stultz@...aro.org>,
        Wangbinghui <wangbinghui@...ilicon.com>
Subject: Re: [PATCH v1 05/12] usb: dwc3: Add two quirks for Hisilicon Kirin
 Soc Platform

On Mon, Dec 3, 2018 at 5:48 AM Yu Chen <chenyu56@...wei.com> wrote:
>
> There are tow quirks for DesignWare USB3 DRD Core of Hisilicon Kirin Soc.
> 1)SPLIT_BOUNDARY_DISABLE should be set for Host mode
> 2)A GCTL soft reset should be executed when switch mode

> +static void dwc3_gctl_core_soft_reset(struct dwc3 *dwc)
> +{

> +       int reg;

u32? int for register value looks confusing a bit.

> +       reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> +       reg |= (DWC3_GCTL_CORESOFTRESET);
> +       dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> +
> +       reg = dwc3_readl(dwc->regs, DWC3_GCTL);
> +       reg &= ~(DWC3_GCTL_CORESOFTRESET);
> +       dwc3_writel(dwc->regs, DWC3_GCTL, reg);
> +}

> +       int reg;

Ditto.

-- 
With Best Regards,
Andy Shevchenko