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Message-ID: <20181203112200.18220-2-jiada_wang@mentor.com>
Date: Mon, 3 Dec 2018 20:21:55 +0900
From: <jiada_wang@...tor.com>
To: <broonie@...nel.org>, <perex@...ex.cz>, <tiwai@...e.com>,
<kuninori.morimoto.gx@...esas.com>, <vladimir_zapolskiy@...tor.com>
CC: <alsa-devel@...a-project.org>, <linux-kernel@...r.kernel.org>
Subject: [PATCH linux-next v2 1/6] clk: renesas: r8a7795: Add ADG clock
From: Takeshi Kihara <takeshi.kihara.df@...esas.com>
This patch adds ADG clock to the R8A7795 SoC.
Signed-off-by: Takeshi Kihara <takeshi.kihara.df@...esas.com>
Signed-off-by: Jiada Wang <jiada_wang@...tor.com>
---
drivers/clk/renesas/r8a7795-cpg-mssr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/renesas/r8a7795-cpg-mssr.c b/drivers/clk/renesas/r8a7795-cpg-mssr.c
index 119c02440726..813288099c84 100644
--- a/drivers/clk/renesas/r8a7795-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a7795-cpg-mssr.c
@@ -237,6 +237,7 @@ static struct mssr_mod_clk r8a7795_mod_clks[] __initdata = {
DEF_MOD("can-if0", 916, R8A7795_CLK_S3D4),
DEF_MOD("i2c6", 918, R8A7795_CLK_S0D6),
DEF_MOD("i2c5", 919, R8A7795_CLK_S0D6),
+ DEF_MOD("adg", 922, R8A7795_CLK_S0D1),
DEF_MOD("i2c-dvfs", 926, R8A7795_CLK_CP),
DEF_MOD("i2c4", 927, R8A7795_CLK_S0D6),
DEF_MOD("i2c3", 928, R8A7795_CLK_S0D6),
--
2.17.0
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