linux-kernel - RE: [PATCHv2 3/6] PCI: layerscape: Add the EP mode support

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Message-ID: <HE1PR04MB1497E4A26E7902E5EAB15D36F5AE0@HE1PR04MB1497.eurprd04.prod.outlook.com>
Date:   Mon, 3 Dec 2018 04:10:12 +0000
From:   Xiaowei Bao <xiaowei.bao@....com>
To:     Lorenzo Pieralisi <lorenzo.pieralisi@....com>
CC:     "bhelgaas@...gle.com" <bhelgaas@...gle.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Leo Li <leoyang.li@....com>, "kishon@...com" <kishon@...com>,
        "arnd@...db.de" <arnd@...db.de>,
        "gregkh@...uxfoundation.org" <gregkh@...uxfoundation.org>,
        "M.h. Lian" <minghuan.lian@....com>,
        Mingkai Hu <mingkai.hu@....com>, Roy Zang <roy.zang@....com>,
        "kstewart@...uxfoundation.org" <kstewart@...uxfoundation.org>,
        "cyrille.pitchen@...e-electrons.com" 
        <cyrille.pitchen@...e-electrons.com>,
        "pombredanne@...b.com" <pombredanne@...b.com>,
        "shawn.lin@...k-chips.com" <shawn.lin@...k-chips.com>,
        "linux-pci@...r.kernel.org" <linux-pci@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linuxppc-dev@...ts.ozlabs.org" <linuxppc-dev@...ts.ozlabs.org>
Subject: RE: [PATCHv2 3/6] PCI: layerscape: Add the EP mode support

Hi Lorenzo,

-----Original Message-----
From: Lorenzo Pieralisi <lorenzo.pieralisi@....com> 
Sent: 2018年11月30日 18:55
To: Xiaowei Bao <xiaowei.bao@....com>
Cc: bhelgaas@...gle.com; robh+dt@...nel.org; mark.rutland@....com; shawnguo@...nel.org; Leo Li <leoyang.li@....com>; kishon@...com; arnd@...db.de; gregkh@...uxfoundation.org; M.h. Lian <minghuan.lian@....com>; Mingkai Hu <mingkai.hu@....com>; Roy Zang <roy.zang@....com>; kstewart@...uxfoundation.org; cyrille.pitchen@...e-electrons.com; pombredanne@...b.com; shawn.lin@...k-chips.com; niklas.cassel@...s.com; linux-pci@...r.kernel.org; devicetree@...r.kernel.org; linux-kernel@...r.kernel.org; linux-arm-kernel@...ts.infradead.org; linuxppc-dev@...ts.ozlabs.org
Subject: Re: [PATCHv2 3/6] PCI: layerscape: Add the EP mode support

On Mon, Nov 05, 2018 at 04:46:50PM +0800, Xiaowei Bao wrote:
> Add the EP mode support.
> 
> Signed-off-by: Xiaowei Bao <xiaowei.bao@....com>
> ---
> v2:
>  - Add the SoC specific compatibles.
> 
>  .../devicetree/bindings/pci/layerscape-pci.txt     |    3 +++
>  1 files changed, 3 insertions(+), 0 deletions(-)

Wrong commit $SUBJECT, this is not PCI code, it is a DT binding update, I will have a look at the rest of the series to see if I can update this patch or you will do it with the next respin.

Lorenzo
[Xiaowei Bao] HI Lorenzo, thanks a lot, I will send V3 patch to modify the commits. 

> diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt 
> b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> index 66df1e8..9c090c7 100644
> --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> @@ -13,12 +13,15 @@ information.
>  
>  Required properties:
>  - compatible: should contain the platform identifier such as:
> +  RC mode:
>          "fsl,ls1021a-pcie", "snps,dw-pcie"
>          "fsl,ls2080a-pcie", "fsl,ls2085a-pcie", "snps,dw-pcie"
>          "fsl,ls2088a-pcie"
>          "fsl,ls1088a-pcie"
>          "fsl,ls1046a-pcie"
>          "fsl,ls1012a-pcie"
> +  EP mode:
> +        "fsl,ls1046a-pcie-ep", "fsl,ls-pcie-ep"
>  - reg: base addresses and lengths of the PCIe controller register blocks.
>  - interrupts: A list of interrupt outputs of the controller. Must contain an
>    entry for each entry in the interrupt-names property.
> --
> 1.7.1
>