linux-kernel - Re: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe Gen4 controller

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Wed, 5 Dec 2018 16:40:49 -0600
From:   Rob Herring <robh@...nel.org>
To:     "Z.Q. Hou" <zhiqiang.hou@....com>
Cc:     linux-pci@...r.kernel.org,
        "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" 
        <linux-arm-kernel@...ts.infradead.org>, devicetree@...r.kernel.org,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        Mark Rutland <mark.rutland@....com>,
        Subrahmanya Lingappa <l.subrahmanya@...iveil.co.in>,
        Shawn Guo <shawnguo@...nel.org>,
        Yang-Leo Li <leoyang.li@....com>,
        Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
        Catalin Marinas <catalin.marinas@....com>,
        Will Deacon <will.deacon@....com>,
        Mingkai Hu <mingkai.hu@....com>,
        Minghuan Lian <minghuan.lian@....com>,
        Xiaowei Bao <xiaowei.bao@....com>
Subject: Re: [PATCHv2 22/25] dt-bindings: pci: Add NXP Layerscape SoCs PCIe
 Gen4 controller

On Wed, Dec 5, 2018 at 4:38 PM Rob Herring <robh@...nel.org> wrote:
>
> On Tue, Nov 20, 2018 at 09:27:51AM +0000, Z.q. Hou wrote:
> > From: Hou Zhiqiang <Zhiqiang.Hou@....com>
> >
> > Add PCIe Gen4 controller DT bindings of NXP Layerscape SoCs.
> >
> > Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@....com>
> > ---
> > V2:
> >  - Change to use the layerscape-pci.txt for PCIe Gen4 controller
> >    dt-bindings
>
> Sorry someone suggested this, but it seems there's no point in having
> these in the same file. New IP block, do a new file.
>
> >
> >  .../bindings/pci/layerscape-pci.txt           | 57 +++++++++++++++++++
> >  MAINTAINERS                                   |  8 +++
> >  2 files changed, 65 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/pci/layerscape-pci.txt b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > index 66df1e81e0b8..3ef8836b6e97 100644
> > --- a/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/layerscape-pci.txt
> > @@ -1,4 +1,6 @@
> > +====================================
> >  Freescale Layerscape PCIe controller
> > +====================================
> >
> >  This PCIe host controller is based on the Synopsys DesignWare PCIe IP
> >  and thus inherits all the common properties defined in designware-pcie.txt.
> > @@ -58,3 +60,58 @@ Example:
> >                               <0000 0 0 3 &gic GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
> >                               <0000 0 0 4 &gic GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>;
> >       };
> > +
> > +===================================
> > +NXP Layerscape PCIe Gen4 controller
> > +===================================
> > +
> > +This PCIe controller is based on the Mobiveil PCIe IP and thus inherits all
> > +the common properties defined in mobiveil-pcie.txt.
> > +
> > +Required properties:
> > +- compatible: should contain the platform identifier such as:
> > +  "fsl,lx2160a-pcie"
> > +- reg: base addresses and lengths of the PCIe controller register blocks.
> > +  "config_axi_slave": PCIe controller registers
> > +  "csr_axi_slave": Bridge config registers
>
> Wouldn't 'config' and 'csr' be sufficient? And these should be listed
> under reg-names.

NM on the names. I see these are inherited.

Rob