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Message-ID: <154413331679.88331.15909045605070653326@swboyd.mtv.corp.google.com>
Date: Thu, 06 Dec 2018 13:55:16 -0800
From: Stephen Boyd <sboyd@...nel.org>
To: Jeffrey Hugo <jhugo@...eaurora.org>, mark.rutland@....com,
mturquette@...libre.com, robh+dt@...nel.org
Cc: bjorn.andersson@...aro.org, marc.w.gonzalez@...e.fr,
linux-clk@...r.kernel.org, devicetree@...r.kernel.org,
linux-arm-msm@...r.kernel.org, linux-kernel@...r.kernel.org,
Jeffrey Hugo <jhugo@...eaurora.org>
Subject: Re: [PATCH] clk: qcom: smd: Add support for MSM8998 rpm clocks
Quoting Jeffrey Hugo (2018-12-06 13:11:06)
> Add rpm smd clocks, PMIC and bus clocks which are required on MSM8998
> for clients to vote on.
>
> Signed-off-by: Jeffrey Hugo <jhugo@...eaurora.org>
> ---
> .../devicetree/bindings/clock/qcom,rpmcc.txt | 1 +
> drivers/clk/qcom/clk-smd-rpm.c | 62 ++++++++++++++++++++++
> include/dt-bindings/clock/qcom,rpmcc.h | 6 +++
> 3 files changed, 69 insertions(+)
>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> index 87b4949..16c4293 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> +++ b/Documentation/devicetree/bindings/clock/qcom,rpmcc.txt
> @@ -17,6 +17,7 @@ Required properties :
> "qcom,rpmcc-apq8064", "qcom,rpmcc"
> "qcom,rpmcc-msm8996", "qcom,rpmcc"
> "qcom,rpmcc-qcs404", "qcom,rpmcc"
> + "qcom,rpmcc-msm8998", "qcom,rpmcc"
Can you keep this sorted on the first compatible?
>
> - #clock-cells : shall contain 1
>
Rob may prefer this file is split from the driver part into a different
patch.
> diff --git a/drivers/clk/qcom/clk-smd-rpm.c b/drivers/clk/qcom/clk-smd-rpm.c
> index d3aadae..269304e 100644
> --- a/drivers/clk/qcom/clk-smd-rpm.c
> +++ b/drivers/clk/qcom/clk-smd-rpm.c
> @@ -655,11 +655,73 @@ static int clk_smd_rpm_enable_scaling(struct qcom_smd_rpm *rpm)
> .num_clks = ARRAY_SIZE(qcs404_clks),
> };
>
> +/* msm8998 */
> +DEFINE_CLK_SMD_RPM(msm8998, snoc_clk, snoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 1);
> +DEFINE_CLK_SMD_RPM(msm8998, cnoc_clk, cnoc_a_clk, QCOM_SMD_RPM_BUS_CLK, 2);
> +DEFINE_CLK_SMD_RPM(msm8998, ce1_clk, ce1_a_clk, QCOM_SMD_RPM_CE_CLK, 0);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, div_clk1, div_clk1_a, 0xb);
> +DEFINE_CLK_SMD_RPM(msm8998, ipa_clk, ipa_a_clk, QCOM_SMD_RPM_IPA_CLK, 0);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, bb_clk1, bb_clk1_a, 1);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, bb_clk2, bb_clk2_a, 2);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, bb_clk3_pin, bb_clk3_a_pin, 3);
> +DEFINE_CLK_SMD_RPM(msm8998, mmssnoc_axi_rpm_clk, mmssnoc_axi_rpm_a_clk,
> + QCOM_SMD_RPM_MMAXI_CLK, 0);
> +DEFINE_CLK_SMD_RPM(msm8998, aggre1_noc_clk, aggre1_noc_a_clk,
> + QCOM_SMD_RPM_AGGR_CLK, 1);
> +DEFINE_CLK_SMD_RPM(msm8998, aggre2_noc_clk, aggre2_noc_a_clk,
> + QCOM_SMD_RPM_AGGR_CLK, 2);
> +DEFINE_CLK_SMD_RPM_QDSS(msm8998, qdss_clk, qdss_a_clk,
> + QCOM_SMD_RPM_MISC_CLK, 1);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk1, rf_clk1_a, 4);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk2_pin, rf_clk2_a_pin, 5);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER(msm8998, rf_clk3, rf_clk3_a, 6);
> +DEFINE_CLK_SMD_RPM_XO_BUFFER_PINCTRL(msm8998, rf_clk3_pin, rf_clk3_a_pin, 6);
> +static struct clk_smd_rpm *msm8998_clks[] = {
> + [RPM_SMD_SNOC_CLK] = &msm8998_snoc_clk,
> + [RPM_SMD_SNOC_A_CLK] = &msm8998_snoc_a_clk,
> + [RPM_SMD_CNOC_CLK] = &msm8998_cnoc_clk,
> + [RPM_SMD_CNOC_A_CLK] = &msm8998_cnoc_a_clk,
> + [RPM_SMD_CE1_CLK] = &msm8998_ce1_clk,
> + [RPM_SMD_CE1_A_CLK] = &msm8998_ce1_a_clk,
> + [RPM_SMD_DIV_CLK1] = &msm8998_div_clk1,
> + [RPM_SMD_DIV_A_CLK1] = &msm8998_div_clk1_a,
> + [RPM_SMD_IPA_CLK] = &msm8998_ipa_clk,
> + [RPM_SMD_IPA_A_CLK] = &msm8998_ipa_a_clk,
> + [RPM_SMD_BB_CLK1] = &msm8998_bb_clk1,
> + [RPM_SMD_BB_CLK1_A] = &msm8998_bb_clk1_a,
> + [RPM_SMD_BB_CLK2] = &msm8998_bb_clk2,
> + [RPM_SMD_BB_CLK2_A] = &msm8998_bb_clk2_a,
> + [RPM_SMD_BB_CLK3_PIN] = &msm8998_bb_clk3_pin,
> + [RPM_SMD_BB_CLK3_A_PIN] = &msm8998_bb_clk3_a_pin,
> + [RPM_SMD_MMAXI_CLK] = &msm8998_mmssnoc_axi_rpm_clk,
> + [RPM_SMD_MMAXI_A_CLK] = &msm8998_mmssnoc_axi_rpm_a_clk,
> + [RPM_SMD_AGGR1_NOC_CLK] = &msm8998_aggre1_noc_clk,
> + [RPM_SMD_AGGR1_NOC_A_CLK] = &msm8998_aggre1_noc_a_clk,
> + [RPM_SMD_AGGR2_NOC_CLK] = &msm8998_aggre2_noc_clk,
> + [RPM_SMD_AGGR2_NOC_A_CLK] = &msm8998_aggre2_noc_a_clk,
> + [RPM_SMD_QDSS_CLK] = &msm8998_qdss_clk,
> + [RPM_SMD_QDSS_A_CLK] = &msm8998_qdss_a_clk,
> + [RPM_SMD_RF_CLK1] = &msm8998_rf_clk1,
> + [RPM_SMD_RF_CLK1_A] = &msm8998_rf_clk1_a,
> + [RPM_SMD_RF_CLK2_PIN] = &msm8998_rf_clk2_pin,
> + [RPM_SMD_RF_CLK2_A_PIN] = &msm8998_rf_clk2_a_pin,
> + [RPM_SMD_RF_CLK3] = &msm8998_rf_clk3,
> + [RPM_SMD_RF_CLK3_A] = &msm8998_rf_clk3_a,
> + [RPM_SMD_RF_CLK3_PIN] = &msm8998_rf_clk3_pin,
> + [RPM_SMD_RF_CLK3_A_PIN] = &msm8998_rf_clk3_a_pin,
> +};
> +
> +static const struct rpm_smd_clk_desc rpm_clk_msm8998 = {
> + .clks = msm8998_clks,
> + .num_clks = ARRAY_SIZE(msm8998_clks),
> +};
> +
> static const struct of_device_id rpm_smd_clk_match_table[] = {
> { .compatible = "qcom,rpmcc-msm8916", .data = &rpm_clk_msm8916 },
> { .compatible = "qcom,rpmcc-msm8974", .data = &rpm_clk_msm8974 },
> { .compatible = "qcom,rpmcc-msm8996", .data = &rpm_clk_msm8996 },
> { .compatible = "qcom,rpmcc-qcs404", .data = &rpm_clk_qcs404 },
> + { .compatible = "qcom,rpmcc-msm8998", .data = &rpm_clk_msm8998 },
And this sorted too.
> { }
> };
> MODULE_DEVICE_TABLE(of, rpm_smd_clk_match_table);
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