linux-kernel - Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller driver

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Message-ID: <c7fe7eb3-b13d-2e90-12de-3edeadd9d5b0@gmail.com>
Date:   Thu, 6 Dec 2018 10:19:10 +0100
From:   Marek Vasut <marek.vasut@...il.com>
To:     masonccyang@...c.com.tw
Cc:     Boris Brezillon <boris.brezillon@...tlin.com>,
        Mark Brown <broonie@...nel.org>,
        Geert Uytterhoeven <geert@...ux-m68k.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Simon Horman <horms@...ge.net.au>, juliensu@...c.com.tw,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>,
        linux-spi <linux-spi@...r.kernel.org>, zhengxunli@...c.com.tw
Subject: Re: [PATCH v2 1/2] spi: Add Renesas R-Car Gen3 RPC SPI controller
 driver

On 12/06/2018 10:17 AM, masonccyang@...c.com.tw wrote:
> Hi Marek,

Hi,

>> >> > +
>> >> > +       pm_runtime_enable(&pdev->dev);
>> >> > +       master->auto_runtime_pm = true;
>> >> > +
>> >> > +       master->num_chipselect = 1;
>> >> > +       master->mem_ops = &rpc_spi_mem_ops;
>> >> > +       master->transfer_one_message = rpc_spi_transfer_one_message;
>> >>
>> >> Is there any reason you cannot use the standard
>> >> spi_transfer_one_message, i.e. provide spi_controller.transfer_one()
>> >> instead of spi_controller.transfer_one_message()?
>> >>
>> >
>> > It seems there is a RPC HW restriction in CS# pin control.
>> > Therefore, it can't send the 1'st spi-transfer for command and then
>> > keeping CS# pin goes low for the 2'nd spi-transfer for address/data and
>> > so on.
>>
>> Isn't register DRCR bit SSLN/SSLE exactly for this purpose ?
>>
> 
> DRCR is for RPC module works in external space read mode, using memcpy( ).
> It is not for _spi_sync().
> 
> I only could use manual I/O mode by SMCR@...-8 SSLKP and I found it has
> some
> restrictions in manual I/O mode to control CS# pin.

What restrictions are those ? I am aware of some, maybe there is more.

-- 
Best regards,
Marek Vasut