linux-kernel - Re: [Linux-stm32] [ v3 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2 NAND flash controller driver

Open Source and information security mailing list archives

Message-ID: <dafcda21-fceb-1577-7f1c-41f1009b99a7@st.com>
Date:   Fri, 7 Dec 2018 10:21:38 +0000
From:   Benjamin GAIGNARD <benjamin.gaignard@...com>
To:     Linus Walleij <linus.walleij@...aro.org>,
        Christophe KERELLO <christophe.kerello@...com>
CC:     Mark Rutland <mark.rutland@....com>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Boris Brezillon <boris.brezillon@...tlin.com>,
        Richard Weinberger <richard@....at>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        Mark Vasut <marek.vasut@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        "linux-mtd@...ts.infradead.org" <linux-mtd@...ts.infradead.org>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Brian Norris <computersforpeace@...il.com>,
        David Woodhouse <dwmw2@...radead.org>,
        "linux-stm32@...md-mailman.stormreply.com" 
        <linux-stm32@...md-mailman.stormreply.com>
Subject: Re: [Linux-stm32] [ v3 2/3] mtd: rawnand: stm32_fmc2: add STM32 FMC2
 NAND flash controller driver

On 12/7/18 10:06 AM, Linus Walleij wrote:
> Hi Christophe,
>
> On Thu, Nov 29, 2018 at 5:42 PM Christophe Kerello
> <christophe.kerello@...com> wrote:
>
>> +/* FMC2 Controller Registers */
>> +#define FMC2_BCR1                      0x0
>> +#define FMC2_PCR                       0x80
> (...)
>> +/* Register: FMC2_BCR1 */
>> +#define FMC2_BCR1_FMC2EN               BIT(31)
> Well this looks like an especially clever register map and a specific choice
> of bit 31 in the fist register to activate FMC2. Registers 0x04 thru
> 0x7c are completely unused save for one bit.
>
> It's almost like this is the good old FSMC integrated in parallel with FMC2,
> so that if you don't set bit 31, this becomes something that can be used
> with drivers/mtd/nand/raw/fsmc_nand.c, and FMC2 mode is activated
> by setting this bit, activating all the new registers.
>
> It wouldn't surprise me given how HW designers like to work.
>
> Is this the case?

No, it is the same story than for stmfx driver, it looks to be the same 
from registers

point of view but internal hardware block design is completely different.

>
> If that is the case I think it should at least be mentioned in commit
> logs and DT bindings and possibly in a comment on the driver
> itself.
>
> Yours,
> Linus Walleij
> _______________________________________________
> Linux-stm32 mailing list
> Linux-stm32@...md-mailman.stormreply.com
> https://st-md-mailman.stormreply.com/mailman/listinfo/linux-stm32

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives