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Message-Id: <20181207175151.8969-3-manivannan.sadhasivam@linaro.org>
Date: Fri, 7 Dec 2018 23:21:50 +0530
From: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
To: vinholikatti@...il.com, jejb@...ux.vnet.ibm.com,
martin.petersen@...cle.com, liwei213@...wei.com, robh+dt@...nel.org
Cc: linux-scsi@...r.kernel.org, linux-kernel@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
john.stultz@...aro.org, amit.kucheria@...aro.org,
guodong.xu@...aro.org,
Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
Subject: [PATCH 2/3] arm64: dts: hisilicon: hi3670: Add UFS controller support
Add UFS controller support for HiSilicon HI3670 SoC.
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@...aro.org>
---
arch/arm64/boot/dts/hisilicon/hi3670.dtsi | 18 ++++++++++++++++++
1 file changed, 18 insertions(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
index 6ccdf5040ffd..285219dd657f 100644
--- a/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi3670.dtsi
@@ -654,6 +654,24 @@
clock-names = "apb_pclk";
};
+ /* UFS */
+ ufs: ufs@...c0000 {
+ compatible = "hisilicon,hi3670-ufs", "jedec,ufs-2.1";
+ /* 0: HCI standard */
+ /* 1: UFS SYS CTRL */
+ reg = <0x0 0xff3c0000 0x0 0x1000>,
+ <0x0 0xff3e0000 0x0 0x1000>;
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_SPI 278 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&crg_ctrl HI3670_CLK_GATE_UFSIO_REF>,
+ <&crg_ctrl HI3670_CLK_GATE_UFS_SUBSYS>;
+ clock-names = "ref_clk", "phy_clk";
+ freq-table-hz = <0 0>, <0 0>;
+ /* offset: 0x84; bit: 12 */
+ resets = <&crg_rst 0x84 12>;
+ reset-names = "rst";
+ };
+
/* SD */
dwmmc1: dwmmc1@...7f000 {
compatible = "hisilicon,hi3670-dw-mshc";
--
2.17.1
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