linux-kernel - Re: [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal SPI controller

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Message-ID: <f6c3a649-f580-513d-644d-5010b3b5cf0b@ti.com>
Date:   Mon, 10 Dec 2018 16:49:29 +0530
From:   Vignesh R <vigneshr@...com>
To:     Boris Brezillon <boris.brezillon@...tlin.com>
CC:     Marek Vasut <marek.vasut@...il.com>,
        Rob Herring <robh+dt@...nel.org>,
        Brian Norris <computersforpeace@...il.com>,
        Yogesh Gaur <yogeshnarayan.gaur@....com>,
        Linux ARM Mailing List <linux-arm-kernel@...ts.infradead.org>,
        <linux-mtd@...ts.infradead.org>, <devicetree@...r.kernel.org>,
        <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH 3/3] mtd: spi-nor: cadence-quadspi: Add support for Octal
 SPI controller

On 10/12/18 2:15 PM, Boris Brezillon wrote:
> On Wed, 3 Oct 2018 22:26:03 +0530
> Vignesh R <vigneshr@...com> wrote:
> 
>> Cadence OSPI controller IP supports Octal IO (x8 IO lines),
>> It also has an integrated PHY. IP register layout is very
>> similar to existing QSPI IP except for additional bits to support Octal
>> and Octal DDR mode. Therefore, extend current driver to support Octal
>> mode.
>>
>> Signed-off-by: Vignesh R <vigneshr@...com>
>> ---
>>  drivers/mtd/spi-nor/cadence-quadspi.c | 9 +++++++++
>>  1 file changed, 9 insertions(+)
>>
>> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c
>> index e24db817154e..48b00e75a879 100644
>> --- a/drivers/mtd/spi-nor/cadence-quadspi.c
>> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c
>> @@ -101,6 +101,7 @@ struct cqspi_st {
>>  #define CQSPI_INST_TYPE_SINGLE			0
>>  #define CQSPI_INST_TYPE_DUAL			1
>>  #define CQSPI_INST_TYPE_QUAD			2
>> +#define CQSPI_INST_TYPE_OCTAL			3
>>  
>>  #define CQSPI_DUMMY_CLKS_PER_BYTE		8
>>  #define CQSPI_DUMMY_BYTES_MAX			4
>> @@ -898,6 +899,9 @@ static int cqspi_set_protocol(struct spi_nor *nor, const int read)
>>  		case SNOR_PROTO_1_1_4:
>>  			f_pdata->data_width = CQSPI_INST_TYPE_QUAD;
>>  			break;
>> +		case SNOR_PROTO_1_1_8:
>> +			f_pdata->data_width = CQSPI_INST_TYPE_OCTAL;
>> +			break;
>>  		default:
>>  			return -EINVAL;
>>  		}
>> @@ -1205,6 +1209,7 @@ static int cqspi_setup_flash(struct cqspi_st *cqspi, struct device_node *np)
>>  			SNOR_HWCAPS_READ_FAST |
>>  			SNOR_HWCAPS_READ_1_1_2 |
>>  			SNOR_HWCAPS_READ_1_1_4 |
>> +			SNOR_HWCAPS_READ_1_1_8 |
> 
> Is this really supported on qspi versions of this IP? I guess not given
> the description in the commit message and the name of the new
> compatible (ospi instead of qspi).

No, qspi version does not support Octal mode. I guess you are pointing
out its logically wrong for driver with "*-qspi" compatible to declare
SNOR_HWCAPS_READ_1_1_8 capability.
Will update patch to declare SNOR_HWCAPS_READ_1_1_8 based on compatible.

> 
>>  			SNOR_HWCAPS_PP,
>>  	};
>>  	struct platform_device *pdev = cqspi->pdev;
>> @@ -1456,6 +1461,10 @@ static const struct of_device_id cqspi_dt_ids[] = {
>>  		.compatible = "ti,k2g-qspi",
>>  		.data = (void *)CQSPI_NEEDS_WR_DELAY,
>>  	},
>> +	{
>> +		.compatible = "ti,am654-ospi",
>> +		.data = (void *)CQSPI_NEEDS_WR_DELAY,
>> +	},
>>  	{ /* end of table */ }
>>  };
>>  
> 

-- 
Regards
Vignesh