linux-kernel - [PATCH] ARM: dts: ls1021a: Add memory controller

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Message-Id: <20181211154834.4489-1-patrick.havelange@essensium.com>
Date:   Tue, 11 Dec 2018 16:48:34 +0100
From:   Patrick Havelange <patrick.havelange@...ensium.com>
To:     Shawn Guo <shawnguo@...nel.org>, Li Yang <leoyang.li@....com>,
        Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        linux-arm-kernel@...ts.infradead.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org, Borislav Petkov <bp@...en8.de>,
        Mauro Carvalho Chehab <mchehab@...nel.org>,
        linux-edac@...r.kernel.org
Cc:     arnout.vandecappelle@...ensium.com,
        patrick.havelange@...ensium.com, matthew.weber@...kwellcollins.com
Subject: [PATCH] ARM: dts: ls1021a: Add memory controller

The LS1021A has a memory controller that supports EDAC. This commit
adds an entry for it.

Signed-off-by: Patrick Havelange <patrick.havelange@...ensium.com>
---
 arch/arm/boot/dts/ls1021a.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index bdd6e66a79ad..a877c32bff20 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -125,6 +125,13 @@
 		interrupt-parent = <&gic>;
 		ranges;
 
+		ddr: memory-controller@...0000 {
+			compatible = "fsl,qoriq-memory-controller";
+			reg = <0x0 0x1080000 0x0 0x1000>;
+			interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>;
+			big-endian;
+		};
+
 		gic: interrupt-controller@...0000 {
 			compatible = "arm,gic-400", "arm,cortex-a7-gic";
 			#interrupt-cells = <3>;
-- 
2.17.1