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Date: Wed, 12 Dec 2018 17:18:46 +0000
From: Jonathan Cameron <jic23@...nel.org>
To: Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>
Cc: knaack.h@....de, lars@...afoo.de, pmeerw@...erw.net,
kgene@...nel.org, krzk@...nel.org, xc-racer2@...e.ca,
broonie@...nel.org, arnaud.pouliquen@...com,
baolin.wang@...aro.org, smohanad@...eaurora.org,
eugen.hristev@...rochip.com, rdunlap@...radead.org,
vilhelm.gray@...il.com, freeman.liu@...eadtrum.com,
marcus.folkesson@...il.com, geert@...ux-m68k.org,
robh+dt@...nel.org, mark.rutland@....com,
devicetree@...r.kernel.org, linux-iio@...r.kernel.org,
linux-arm-kernel@...ts.infradead.org,
linux-samsung-soc@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH 1/3] iio: adc: exynos-adc: Add S5PV210 variant
On Fri, 7 Dec 2018 20:11:34 +0100
Paweł Chmiel <pawel.mikolaj.chmiel@...il.com> wrote:
> From: Jonathan Bakker <xc-racer2@...e.ca>
>
> S5PV210's ADC variant is almost the same as v1 except that it has 10
> channels and doesn't require the pmu register
>
> Signed-off-by: Jonathan Bakker <xc-racer2@...e.ca>
> Signed-off-by: Paweł Chmiel <pawel.mikolaj.chmiel@...il.com>
Long enough I thing ;)
Applied to the togreg branch of iio.git and pushed out as testing
for the autobuilders to play with it.
Thanks,
Jonathan
> ---
> drivers/iio/adc/exynos_adc.c | 14 ++++++++++++++
> 1 file changed, 14 insertions(+)
>
> diff --git a/drivers/iio/adc/exynos_adc.c b/drivers/iio/adc/exynos_adc.c
> index f10443f92e4c..fa2d2b5767f3 100644
> --- a/drivers/iio/adc/exynos_adc.c
> +++ b/drivers/iio/adc/exynos_adc.c
> @@ -115,6 +115,7 @@
> #define MAX_ADC_V2_CHANNELS 10
> #define MAX_ADC_V1_CHANNELS 8
> #define MAX_EXYNOS3250_ADC_CHANNELS 2
> +#define MAX_S5PV210_ADC_CHANNELS 10
>
> /* Bit definitions common for ADC_V1 and ADC_V2 */
> #define ADC_CON_EN_START (1u << 0)
> @@ -282,6 +283,16 @@ static const struct exynos_adc_data exynos_adc_v1_data = {
> .start_conv = exynos_adc_v1_start_conv,
> };
>
> +static const struct exynos_adc_data exynos_adc_s5pv210_data = {
> + .num_channels = MAX_S5PV210_ADC_CHANNELS,
> + .mask = ADC_DATX_MASK, /* 12 bit ADC resolution */
> +
> + .init_hw = exynos_adc_v1_init_hw,
> + .exit_hw = exynos_adc_v1_exit_hw,
> + .clear_irq = exynos_adc_v1_clear_irq,
> + .start_conv = exynos_adc_v1_start_conv,
> +};
> +
> static void exynos_adc_s3c2416_start_conv(struct exynos_adc *info,
> unsigned long addr)
> {
> @@ -478,6 +489,9 @@ static const struct of_device_id exynos_adc_match[] = {
> }, {
> .compatible = "samsung,s3c6410-adc",
> .data = &exynos_adc_s3c64xx_data,
> + }, {
> + .compatible = "samsung,s5pv210-adc",
> + .data = &exynos_adc_s5pv210_data,
> }, {
> .compatible = "samsung,exynos-adc-v1",
> .data = &exynos_adc_v1_data,
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