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Message-Id: <1544742869-19980-1-git-send-email-atish.patra@wdc.com>
Date: Thu, 13 Dec 2018 15:14:25 -0800
From: Atish Patra <atish.patra@....com>
To: linux-kernel@...r.kernel.org
Cc: Atish Patra <atish.patra@....com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
devicetree@...r.kernel.org,
Dmitriy Cherkasov <dmitriy@...-tech.org>,
linux-riscv@...ts.infradead.org,
Mark Rutland <mark.rutland@....com>,
Palmer Dabbelt <palmer@...ive.com>,
Rob Herring <robh+dt@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Anup Patel <anup@...infault.org>,
Damien Le Moal <Damien.LeMoal@....com>,
Christoph Hellwig <hch@...radead.org>
Subject: [PATCH v2 0/4] Timer code cleanup.
This patch series provides an assorted timer cleanups in RISC-V.
Changes from v1->v2:
1. Updated commit text in 1/4.
2. Added a timebase check for each cpu.
3. Added a warning for invalid hartid 4/4.
Atish Patra (3):
RISC-V: Support per-hart timebase-frequency
RISC-V: Remove per cpu clocksource
RISC-V: Fix non-smp kernel boot on SMP systems
Palmer Dabbelt (1):
dt-bindings: Correct RISC-V's timebase-frequency
Documentation/devicetree/bindings/riscv/cpus.txt | 4 +-
arch/riscv/kernel/time.c | 9 +----
drivers/clocksource/riscv_timer.c | 51 +++++++++++++++++++++---
3 files changed, 49 insertions(+), 15 deletions(-)
--
2.7.4
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