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Message-ID: <20181214153830.GB22063@linux.intel.com>
Date: Fri, 14 Dec 2018 07:38:30 -0800
From: Sean Christopherson <sean.j.christopherson@...el.com>
To: Jethro Beekman <jethro@...tanix.com>
Cc: Andy Lutomirski <luto@...nel.org>,
Thomas Gleixner <tglx@...utronix.de>,
Ingo Molnar <mingo@...hat.com>, Borislav Petkov <bp@...en8.de>,
"x86@...nel.org" <x86@...nel.org>,
Dave Hansen <dave.hansen@...ux.intel.com>,
Peter Zijlstra <peterz@...radead.org>,
Jarkko Sakkinen <jarkko.sakkinen@...ux.intel.com>,
"H. Peter Anvin" <hpa@...or.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-sgx@...r.kernel.org" <linux-sgx@...r.kernel.org>,
Andy Lutomirski <luto@...capital.net>,
Josh Triplett <josh@...htriplett.org>,
Haitao Huang <haitao.huang@...ux.intel.com>,
"Dr . Greg Wettstein" <greg@...ellic.com>
Subject: Re: [RFC PATCH v4 5/5] x86/vdso: Add __vdso_sgx_enter_enclave() to
wrap SGX enclave transitions
On Fri, Dec 14, 2018 at 07:12:04AM -0800, Sean Christopherson wrote:
> On Fri, Dec 14, 2018 at 09:55:49AM +0000, Jethro Beekman wrote:
> > On 2018-12-14 03:01, Sean Christopherson wrote:
> > >+2: pop %rbx
> > >+ pop %r12
> > >+ pop %r13
> > >+ pop %r14
> > >+ pop %r15
> > >+ pop %rbp
> > >+ ret
> >
> > x86-64 ABI requires that you call CLD here (enclave may set it).
>
> Ugh. Technically MXCSR and the x87 CW also need to be preserved.
>
> What if rather than treating the enclave as hostile we require it to be
> compliant with the x86-64 ABI like any other function? That would solve
> the EFLAGS.DF, MXCSR and x87 issues without adding unnecessary overhead.
> And we wouldn't have to save/restore R12-R15. It'd mean we couldn't use
> the stack's red zone to hold @regs and @e, but that's poor form anyways.
Grr, except the processor crushes R12-R15, FCW and MXCSR on asynchronous
exits. But not EFLAGS.DF, that's real helpful.
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