linux-kernel - Re: [PATCH 2/3] clk: imx: imx7ulp: add arm hsrun mode clocks support

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Message-ID: <154482508301.19322.1653003805163251008@swboyd.mtv.corp.google.com>
Date:   Fri, 14 Dec 2018 14:04:43 -0800
From:   Stephen Boyd <sboyd@...nel.org>
To:     "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        "kernel@...gutronix.de" <kernel@...gutronix.de>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "linux-clk@...r.kernel.org" <linux-clk@...r.kernel.org>,
        "linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
        "mark.rutland@....com" <mark.rutland@....com>,
        "mturquette@...libre.com" <mturquette@...libre.com>,
        "robh+dt@...nel.org" <robh+dt@...nel.org>,
        "s.hauer@...gutronix.de" <s.hauer@...gutronix.de>,
        "shawnguo@...nel.org" <shawnguo@...nel.org>,
        Aisheng Dong <aisheng.dong@....com>,
        Anson Huang <anson.huang@....com>,
        Fabio Estevam <fabio.estevam@....com>
Cc:     dl-linux-imx <linux-imx@....com>
Subject: Re: [PATCH 2/3] clk: imx: imx7ulp: add arm hsrun mode clocks support

Quoting Anson Huang (2018-12-07 02:03:34)
> i.MX7ULP has a Cortex-A7 CPU which can run in RUN mode
> or HSRUN mode, it is controlled in SMC1 module. The RUN
> mode and HSRUN mode will use different clock source for
> ARM, "divcore" for RUN mode and "hsrun_divcore" for HSRUN
> mode, so the control bits in SMC1 module can be abstracted
> as a HW clock mux, this patch adds HSRUN mode related
> clocks in SCG1 module and adds "arm" clock in SMC1 module
> to support RUN mode and HSRUN mode switch.
> 
> Latest clock tree in RUN mode as below:
> 
>  firc                                 0        0        0    48000000          0     0  50000
>     firc_bus_clk                      0        0        0    48000000          0     0  50000
>     hsrun_scs_sel                     0        0        0    48000000          0     0  50000
>        hsrun_divcore                  0        0        0    48000000          0     0  50000
> 
>  sosc                                 3        3        3    24000000          0     0  50000
>     spll_pre_sel                      1        1        1    24000000          0     0  50000
>        spll_pre_div                   1        1        2    24000000          0     0  50000
>           spll                        1        1        2   528000000          0     0  50000
>              spll_pfd0                1        1        1   500210526          0     0  50000
>                 spll_pfd_sel          1        1        0   500210526          0     0  50000
>                    spll_sel           1        1        0   500210526          0     0  50000
>                       scs_sel         1        1        0   500210526          0     0  50000
>                          divcore      1        1        0   500210526          0     0  50000
>                             arm       1        1        0   500210526          0     0  50000
> 
> Signed-off-by: Anson Huang <Anson.Huang@....com>
> ---

Applied to clk-next