linux-kernel - RE: [PATCH] dt-bindings: PCI: rcar: Add device tree support for r8a774c0

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Message-ID: <TY1PR01MB1770FAF7F451A3B8F4903ED9C0A10@TY1PR01MB1770.jpnprd01.prod.outlook.com>
Date:   Fri, 14 Dec 2018 10:49:16 +0000
From:   Fabrizio Castro <fabrizio.castro@...renesas.com>
To:     Geert Uytterhoeven <geert@...ux-m68k.org>
CC:     Rob Herring <robh+dt@...nel.org>,
        Mark Rutland <mark.rutland@....com>,
        Bjorn Helgaas <bhelgaas@...gle.com>,
        linux-pci <linux-pci@...r.kernel.org>,
        "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" 
        <devicetree@...r.kernel.org>,
        Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
        Simon Horman <horms@...ge.net.au>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Chris Paterson <Chris.Paterson2@...esas.com>,
        Biju Das <biju.das@...renesas.com>,
        Linux-Renesas <linux-renesas-soc@...r.kernel.org>
Subject: RE: [PATCH] dt-bindings: PCI: rcar: Add device tree support for
 r8a774c0

Hello Geert,

Thank you for your feedback!

> From: Geert Uytterhoeven <geert@...ux-m68k.org>
> Sent: 14 December 2018 10:29
> Subject: Re: [PATCH] dt-bindings: PCI: rcar: Add device tree support for r8a774c0
>
> Hi Fabrizio,
>
> On Thu, Dec 13, 2018 at 9:21 PM Fabrizio Castro
> <fabrizio.castro@...renesas.com> wrote:
> > Add PCIe support for the RZ/G2E (a.k.a. R8A774C0).
> >
> > Signed-off-by: Fabrizio Castro <fabrizio.castro@...renesas.com>
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@...der.be>
>
> One question below.
>
> > --- a/Documentation/devicetree/bindings/pci/rcar-pci.txt
> > +++ b/Documentation/devicetree/bindings/pci/rcar-pci.txt
>
> > @@ -37,7 +39,8 @@ compatible: "renesas,pcie-r8a7743" for the R8A7743 SoC;
> >
> >  Optional properties:
> >  - phys: from common PHY binding: PHY phandle and specifier (only make sense
> > -       for R-Car gen3 SoCs where the PCIe PHYs have their own register blocks).
> > +       for R-Car gen3 and RZ/G2 SoCs where the PCIe PHYs have their own
>
> Gen3, while at it?

Can do

>
> > +       register blocks).
>
> The RZ/G2 Hardware User Manual I have lacks the table specifying which SoCs
> have which PHY registers.  So I cannot verify if the above paragraph applies to
> RZ/G2(E).

I'll reply to this on your follow-up  email.

Thanks,
Fab

>
> Gr{oetje,eeting}s,
>
>                         Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
>                                 -- Linus Torvalds


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