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Message-ID: <20181214014701.373b220b@nic.cz>
Date: Fri, 14 Dec 2018 01:47:01 +0100
From: Marek Behun <marek.behun@....cz>
To: Miquel Raynal <miquel.raynal@...tlin.com>
Cc: Gregory Clement <gregory.clement@...tlin.com>,
Jason Cooper <jason@...edaemon.net>,
Andrew Lunn <andrew@...n.ch>,
Sebastian Hesselbarth <sebastian.hesselbarth@...il.com>,
Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
Bjorn Helgaas <bhelgaas@...gle.com>,
<devicetree@...r.kernel.org>, Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Lorenzo Pieralisi <lorenzo.pieralisi@....com>,
linux-pci@...r.kernel.org, <linux-kernel@...r.kernel.org>,
<linux-arm-kernel@...ts.infradead.org>,
Antoine Tenart <antoine.tenart@...tlin.com>,
Maxime Chevallier <maxime.chevallier@...tlin.com>,
Nadav Haklai <nadavh@...vell.com>
Subject: Re: [PATCH v2 03/12] PCI: aardvark: Add PHY support
Hi Miquel,
are there already patches for the A37xx comphy driver?
On Wed, 12 Dec 2018 11:21:33 +0100
Miquel Raynal <miquel.raynal@...tlin.com> wrote:
> The IP needs its PHY to be properly configured to work. While the PHY
> is usually already configured by the bootloader, we will need this
> feature when adding S2RAM support. Take care of registering and
> configuring the PHY from the driver itself.
>
> Suggested-by: Grzegorz Jaszczyk <jaz@...ihalf.com>
> Signed-off-by: Miquel Raynal <miquel.raynal@...tlin.com>
> ---
> drivers/pci/controller/pci-aardvark.c | 62
> +++++++++++++++++++++++++++ 1 file changed, 62 insertions(+)
>
> diff --git a/drivers/pci/controller/pci-aardvark.c
> b/drivers/pci/controller/pci-aardvark.c index
> 1d31d74ddab7..da695572a2ed 100644 ---
> a/drivers/pci/controller/pci-aardvark.c +++
> b/drivers/pci/controller/pci-aardvark.c @@ -17,6 +17,7 @@
> #include <linux/pci.h>
> #include <linux/init.h>
> #include <linux/platform_device.h>
> +#include <linux/phy/phy.h>
> #include <linux/of_address.h>
> #include <linux/of_gpio.h>
> #include <linux/of_pci.h>
> @@ -204,6 +205,7 @@ struct advk_pcie {
> int root_bus_nr;
> struct pci_bridge_emul bridge;
> struct gpio_desc *reset_gpio;
> + struct phy *phy;
> };
>
> static inline void advk_writel(struct advk_pcie *pcie, u32 val, u64
> reg) @@ -1025,6 +1027,62 @@ static int
> advk_pcie_setup_reset_gpio(struct advk_pcie *pcie) return 0;
> }
>
> +static void advk_pcie_disable_phy(struct advk_pcie *pcie)
> +{
> + phy_power_off(pcie->phy);
> + phy_exit(pcie->phy);
> +}
> +
> +static int advk_pcie_enable_phy(struct advk_pcie *pcie)
> +{
> + int ret;
> +
> + if (!pcie->phy)
> + return 0;
> +
> + ret = phy_init(pcie->phy);
> + if (ret)
> + return ret;
> +
> + ret = phy_set_mode(pcie->phy, PHY_MODE_PCIE);
> + if (ret) {
> + phy_exit(pcie->phy);
> + return ret;
> + }
> +
> + ret = phy_power_on(pcie->phy);
> + if (ret) {
> + phy_exit(pcie->phy);
> + return ret;
> + }
> +
> + return 0;
> +}
> +
> +static int advk_pcie_setup_phy(struct advk_pcie *pcie)
> +{
> + struct device *dev = &pcie->pdev->dev;
> + struct device_node *node = dev->of_node;
> + int ret = 0;
> +
> + pcie->phy = devm_of_phy_get(dev, node, NULL);
> + if (IS_ERR(pcie->phy) && (PTR_ERR(pcie->phy) ==
> -EPROBE_DEFER))
> + return PTR_ERR(pcie->phy);
> +
> + /* Old bindings miss the PHY handle */
> + if (IS_ERR(pcie->phy)) {
> + dev_warn(dev, "PHY unavailable (%ld)\n",
> PTR_ERR(pcie->phy));
> + pcie->phy = NULL;
> + return 0;
> + }
> +
> + ret = advk_pcie_enable_phy(pcie);
> + if (ret)
> + dev_err(dev, "Failed to initialize PHY (%d)\n", ret);
> +
> + return ret;
> +}
> +
> static int advk_pcie_probe(struct platform_device *pdev)
> {
> struct device *dev = &pdev->dev;
> @@ -1060,6 +1118,10 @@ static int advk_pcie_probe(struct
> platform_device *pdev) return ret;
> }
>
> + ret = advk_pcie_setup_phy(pcie);
> + if (ret)
> + return ret;
> +
> ret = advk_pcie_setup_reset_gpio(pcie);
> if (ret)
> return ret;
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