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Message-Id: <20181216144715.7486-1-lecopzer@gmail.com>
Date: Sun, 16 Dec 2018 22:47:15 +0800
From: Jian-Lin Chen <lecopzer@...il.com>
To: Julien Thierry <julien.thierry@....com>
Cc: Jian-Lin Chen <lecopzer.chen@...iatek.com>,
linux-arm-kernel@...ts.infradead.org, linux-kernel@...r.kernel.org,
daniel.thompson@...aro.org, joel@...lfernandes.org,
marc.zyngier@....com, christoffer.dall@....com,
james.morse@....com, catalin.marinas@....com, will.deacon@....com,
mark.rutland@....com, Ard Biesheuvel <ard.biesheuvel@...aro.org>,
Oleg Nesterov <oleg@...hat.com>
Subject: Re: [PATCH v7 11/25] arm64: irqflags: Use ICC_PMR_EL1 for interrupt masking
From: Jian-Lin Chen <lecopzer.chen@...iatek.com>
On Wed, 12 Dec 2018 at 17:48, Julien Thierry <julien.thierry@....com> wrote:
> static inline void arch_local_irq_enable(void)
> {
> - asm volatile(
> - "msr daifclr, #2 // arch_local_irq_enable"
> - :
> + unsigned long unmasked = GIC_PRIO_IRQON;
> +
Should we need a WARN_ON() to check if the daif_I bit is masked, or
explicitly unmasked I bit here?
If I bit was masked and someone calls arch_local_irq_enable(), they still
couldn't recieve any interrupt.
> + asm volatile(ALTERNATIVE(
> + "msr daifclr, #2 // arch_local_irq_enable\n"
> + "nop",
> + "msr_s " __stringify(SYS_ICC_PMR_EL1) ",%0\n"
> + "dsb sy",
> + ARM64_HAS_IRQ_PRIO_MASKING)
> :
> + : "r" (unmasked)
> : "memory");
> }
>
> static inline void arch_local_irq_disable(void)
> {
> - asm volatile(
> - "msr daifset, #2 // arch_local_irq_disable"
> - :
> + unsigned long masked = GIC_PRIO_IRQOFF;
> +
> + asm volatile(ALTERNATIVE(
> + "msr daifset, #2 // arch_local_irq_disable",
> + "msr_s " __stringify(SYS_ICC_PMR_EL1) ", %0",
May be a "dsb sy" here?
> + ARM64_HAS_IRQ_PRIO_MASKING)
> :
> + : "r" (masked)
> : "memory");
> }
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