[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <20181217182520.GB7086@infradead.org>
Date: Mon, 17 Dec 2018 10:25:20 -0800
From: Christoph Hellwig <hch@...radead.org>
To: Anup Patel <anup@...infault.org>
Cc: Palmer Dabbelt <palmer@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
Christoph Hellwig <hch@...radead.org>,
Atish Patra <atish.patra@....com>,
linux-riscv@...ts.infradead.org, linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart
base and enable base
On Fri, Nov 30, 2018 at 01:32:02PM +0530, Anup Patel wrote:
> This patch does following optimizations:
> 1. Pre-compute hart base for each context handler
> 2. Pre-compute enable base for each context handler
> 3. Have enable lock for each context handler instead
> of global plic_toggle_lock
All of which is pretty obvious from reading the patch. The big question
that needs to be answered in the changelog is why you do that.
Powered by blists - more mailing lists