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Message-ID: <CAAhSdy11WFLjMGa6PVWdL1=YVQLA_nHB5kA1rBj2FFuk0dOeMw@mail.gmail.com>
Date: Tue, 18 Dec 2018 14:00:21 +0530
From: Anup Patel <anup@...infault.org>
To: Christoph Hellwig <hch@...radead.org>
Cc: Palmer Dabbelt <palmer@...ive.com>,
Albert Ou <aou@...s.berkeley.edu>,
Daniel Lezcano <daniel.lezcano@...aro.org>,
Thomas Gleixner <tglx@...utronix.de>,
Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
Atish Patra <atish.patra@....com>,
linux-riscv@...ts.infradead.org,
"linux-kernel@...r.kernel.org List" <linux-kernel@...r.kernel.org>
Subject: Re: [PATCH v3 1/6] irqchip: sifive-plic: Pre-compute context hart
base and enable base
On Mon, Dec 17, 2018 at 11:55 PM Christoph Hellwig <hch@...radead.org> wrote:
>
> On Fri, Nov 30, 2018 at 01:32:02PM +0530, Anup Patel wrote:
> > This patch does following optimizations:
> > 1. Pre-compute hart base for each context handler
> > 2. Pre-compute enable base for each context handler
> > 3. Have enable lock for each context handler instead
> > of global plic_toggle_lock
>
> All of which is pretty obvious from reading the patch. The big question
> that needs to be answered in the changelog is why you do that.
To compute enable_base and hart_base is two integer additions and
one integer multiplication. This micro-optimization simply avoids this
repeated operations.
Regards,
Anup
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