linux-kernel - Re: Fixing MIPS delay slot emulation weakness?

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 18 Dec 2018 03:13:47 +0200
From:   Aaro Koskinen <aaro.koskinen@....fi>
To:     "Maciej W. Rozycki" <macro@...ux-mips.org>
Cc:     Rich Felker <dalias@...c.org>, Andy Lutomirski <luto@...nel.org>,
        Linux MIPS Mailing List <linux-mips@...ux-mips.org>,
        LKML <linux-kernel@...r.kernel.org>,
        Paul Burton <paul.burton@...tec.com>,
        David Daney <david.daney@...ium.com>,
        Ralf Baechle <ralf@...ux-mips.org>,
        Paul Burton <paul.burton@...s.com>,
        James Hogan <jhogan@...nel.org>
Subject: Re: Fixing MIPS delay slot emulation weakness?

Hi,

On Mon, Dec 17, 2018 at 01:55:28AM +0000, Maciej W. Rozycki wrote:
>  As to actual implementations I believe all the Cavium Octeon line CPUs 
> (David, please correct me if I am wrong) have no FPU and they have vendor 
> extensions beyond the base ISA + ASE instruction set.  Arguably you could 
> say that their additional instructions should not be scheduled into FPU 
> branch delay slots then, however the toolchain will happily do that, as I 
> wrote before.

Octeon III added/introduced FPU.

A.