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Message-Id: <20181219172822.18349-1-lkundrak@v3.sk>
Date: Wed, 19 Dec 2018 18:28:22 +0100
From: Lubomir Rintel <lkundrak@...sk>
To: Thomas Gleixner <tglx@...utronix.de>
Cc: Jason Cooper <jason@...edaemon.net>,
Marc Zyngier <marc.zyngier@....com>,
linux-kernel@...r.kernel.org, Lubomir Rintel <lkundrak@...sk>
Subject: [PATCH v3] irqchip/mmp: only touch the PJ4 & FIQ bits on enable/disable
On an OLPC XO 1.75 machine, the "security processor" handles the GPIO 71
and 72 interrupts. Don't reset the "route to SP" bit (4).
I'm just assuming the bit 4 is the "route to SP" bit -- it fixes the
SP-based keyboard for me and <mach-mmp/regs-icu.h> defines
ICU_INT_ROUTE_SP_IRQ to be 1 << 4. When asked for a data sheet, Marvell
was not helpful.
Signed-off-by: Lubomir Rintel <lkundrak@...sk>
Acked-by: Pavel Machek <pavel@....cz>
---
Changes since v2:
- Correct subsystem maintainers on Cc (irqchip)
Changes since v1:
- Adjusted wording & ack from Pavel
drivers/irqchip/irq-mmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-mmp.c b/drivers/irqchip/irq-mmp.c
index 25f32e1d7764..1ed38f9f1d0a 100644
--- a/drivers/irqchip/irq-mmp.c
+++ b/drivers/irqchip/irq-mmp.c
@@ -190,7 +190,7 @@ static const struct mmp_intc_conf mmp_conf = {
static const struct mmp_intc_conf mmp2_conf = {
.conf_enable = 0x20,
.conf_disable = 0x0,
- .conf_mask = 0x7f,
+ .conf_mask = 0x60,
};
static void __exception_irq_entry mmp_handle_irq(struct pt_regs *regs)
--
2.19.2
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