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Message-Id: <20181219235528.114830-6-mka@chromium.org>
Date: Wed, 19 Dec 2018 15:55:25 -0800
From: Matthias Kaehlcke <mka@...omium.org>
To: Rob Clark <robdclark@...il.com>, David Airlie <airlied@...ux.ie>,
Rob Herring <robh+dt@...nel.org>,
Mark Rutland <mark.rutland@....com>,
Andy Gross <andy.gross@...aro.org>,
David Brown <david.brown@...aro.org>
Cc: linux-arm-msm@...r.kernel.org, dri-devel@...ts.freedesktop.org,
freedreno@...ts.freedesktop.org, devicetree@...r.kernel.org,
linux-kernel@...r.kernel.org,
Archit Taneja <architt@...eaurora.org>,
Sean Paul <seanpaul@...omium.org>,
Rajesh Yadav <ryadav@...eaurora.org>,
Douglas Anderson <dianders@...omium.org>,
Stephen Boyd <swboyd@...omium.org>,
Jeykumar Sankaran <jsanka@...eaurora.org>,
Matthias Kaehlcke <mka@...omium.org>
Subject: [PATCH v5 5/8] drm/msm/dsi: 10nm PHY: Get ref clock from the DT
Get the ref clock of the PHY from the device tree instead of
hardcoding its name and rate.
Note: This change could break old out-of-tree DTS files that
use the 10nm PHY
Signed-off-by: Matthias Kaehlcke <mka@...omium.org>
Reviewed-by: Douglas Anderson <dianders@...omium.org>
---
Changes in v5:
- pass the ref clock name to _register() instead of storing a point
to the clk object in the PLL data structure
Changes in v4:
- none
Changes in v3:
- fixed check for EPROBE_DEFER
- added note to commit message about breaking old DTS files
- added 'Reviewed-by: Douglas Anderson <dianders@...omium.org>' tag
Changes in v2:
- remove anonymous array in clk_init_data assignment
- log error code if devm_clk_get() fails
- don't log devm_clk_get() failures for -EPROBE_DEFER
- updated commit message
---
drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 20 +++++++++++++++++---
1 file changed, 17 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
index 4c03f0b7343ed..adbe5395f4f38 100644
--- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
+++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c
@@ -625,12 +625,14 @@ static void dsi_pll_10nm_destroy(struct msm_dsi_pll *pll)
* state to follow the master PLL's divider/mux state. Therefore, we don't
* require special clock ops that also configure the slave PLL registers
*/
-static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)
+static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm,
+ const char *ref_clk_name)
{
char clk_name[32], parent[32], vco_name[32];
char parent2[32], parent3[32], parent4[32];
+
struct clk_init_data vco_init = {
- .parent_names = (const char *[]){ "xo" },
+ .parent_names = &ref_clk_name,
.num_parents = 1,
.name = vco_name,
.flags = CLK_IGNORE_UNUSED,
@@ -771,6 +773,8 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
{
struct dsi_pll_10nm *pll_10nm;
struct msm_dsi_pll *pll;
+ struct clk *vco_ref_clk;
+ const char *vco_ref_clk_name;
int ret;
if (!pdev)
@@ -786,6 +790,16 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
pll_10nm->id = id;
pll_10nm_list[id] = pll_10nm;
+ vco_ref_clk = devm_clk_get(&pdev->dev, "ref");
+ if (IS_ERR(vco_ref_clk)) {
+ ret = PTR_ERR(vco_ref_clk);
+ if (ret != -EPROBE_DEFER)
+ dev_err(&pdev->dev, "couldn't get 'ref' clock: %d\n",
+ ret);
+ return ERR_PTR(ret);
+ }
+ vco_ref_clk_name = __clk_get_name(vco_ref_clk);
+
pll_10nm->phy_cmn_mmio = msm_ioremap(pdev, "dsi_phy", "DSI_PHY");
if (IS_ERR_OR_NULL(pll_10nm->phy_cmn_mmio)) {
dev_err(&pdev->dev, "failed to map CMN PHY base\n");
@@ -811,7 +825,7 @@ struct msm_dsi_pll *msm_dsi_pll_10nm_init(struct platform_device *pdev, int id)
pll_10nm->vco_delay = 1;
- ret = pll_10nm_register(pll_10nm);
+ ret = pll_10nm_register(pll_10nm, vco_ref_clk_name);
if (ret) {
dev_err(&pdev->dev, "failed to register PLL: %d\n", ret);
return ERR_PTR(ret);
--
2.20.1.415.g653613c723-goog
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