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Message-ID: <20181221081359.GA14707@infradead.org>
Date: Fri, 21 Dec 2018 00:13:59 -0800
From: Christoph Hellwig <hch@...radead.org>
To: Tomasz Figa <tfiga@...omium.org>
Cc: Christoph Hellwig <hch@...radead.org>,
Laurent Pinchart <laurent.pinchart@...asonboard.com>,
"Matwey V. Kornilov" <matwey@....msu.ru>,
Linux Media Mailing List <linux-media@...r.kernel.org>,
Linux Kernel Mailing List <linux-kernel@...r.kernel.org>,
"Matwey V. Kornilov" <matwey.kornilov@...il.com>,
Alan Stern <stern@...land.harvard.edu>,
Ezequiel Garcia <ezequiel@...labora.com>, hdegoede@...hat.com,
Hans Verkuil <hverkuil@...all.nl>,
Mauro Carvalho Chehab <mchehab@...nel.org>,
rostedt@...dmis.org, mingo@...hat.com,
Mike Isely <isely@...ox.com>,
Bhumika Goyal <bhumirks@...il.com>,
Colin King <colin.king@...onical.com>,
Kieran Bingham <kieran.bingham@...asonboard.com>,
keiichiw@...omium.org
Subject: Re: [PATCH v5 2/2] media: usb: pwc: Don't use coherent DMA buffers
for ISO transfer
On Thu, Dec 20, 2018 at 12:23:46PM +0900, Tomasz Figa wrote:
> I haven't been following the problems with virtually tagged cases,
> would you mind sharing some background, so that we can consider it
> when adding non-consistent allocations to VB2?
The problem exists at least partially with the current consistent
allocator, and we need to fix it. My non-coherent series does not have
it, but we would add it if we allowed virtual remapping.
The problem with get_sgtable is that it creates aliasing of kernel
virtual addresses used to access memory and thus the cache. We have
the mapping return from dma_alloc_*, which in case of a remap contains
a vmap/ioremap style address that is different from the kernel direct
mapping address you get from using page_address/kmap on the pages
backing that mapping. (assuming you even have pages - in a few corner
cases we don't and the whole interface concept breaks down).
This creates various problems as the the scatterlist returned from
get_stable now gives a second way to access this memory through direct
mapping addresses in the pages contained in it, but as soon as we do
that we:
a) don't use the nocache mapping used by the coherent allocator if that
is on a per-mapping basis (which it is for many architectures), so
you do get data in the cache even when that might not be assumed
b) if the data returned from dma_alloc_coherent was not actually a
remap but a special pool of non-cached address the cache flushing
instructions might be invalid and caused problems
c) any cache flushing now operates on just those direct mappings, which
in case of the non-coherent allocator and access through the
remapped address does the wrong thing for virtually tagged caches
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