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Message-Id: <20181226183815.81443b67313823e4fd7788eb@magewell.com>
Date: Wed, 26 Dec 2018 18:38:15 +0800
From: Yong <yong.deng@...ewell.com>
To: megous@...ous.com
Cc: 'Ondřej Jirman' via linux-sunxi
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Sakari Ailus <sakari.ailus@...ux.intel.com>
Subject: Re: [linux-sunxi] [PATCH v12 0/2] Initial Allwinner V3s CSI Support
Hi,
On Wed, 26 Dec 2018 11:29:36 +0100
'Ondřej Jirman' via linux-sunxi <linux-sunxi@...glegroups.com> wrote:
> Hello,
>
> On Tue, Oct 30, 2018 at 04:09:48PM +0800, Yong Deng wrote:
> > I can't make v4l2-compliance always happy.
> > The V3s CSI support many pixformats. But they are not always available.
> > It's dependent on the input bus format (MEDIA_BUS_FMT_*).
> > Example:
> > V4L2_PIX_FMT_SBGGR8: MEDIA_BUS_FMT_SBGGR8_1X8
> > V4L2_PIX_FMT_YUYV: MEDIA_BUS_FMT_YUYV8_2X8
> > But I can't get the subdev's format code before starting stream as the
> > subdev may change it. So I can't know which pixformats are available.
> > So I exports all the pixformats supported by SoC.
> > The result is the app (v4l2-compliance) is likely to fail on streamon.
> >
> > This patchset add initial support for Allwinner V3s CSI.
>
> I've tested your patches on A83T and CSI works on that SoC too. I'll send
> DTS patches later.
>
> One thing I noticed is that, when you cat the regmap registers file in debugfs
> while streaming, the kernel locks up hard. I was not able to extract any logs.
May be some registers can't be read when streaming ? Like read-clear regs ?
Or multi CPU core access regs at the same time may cause the bus lock up?
Thanks,
Yong
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